• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.05a
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• pp.227-229
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• 1995

Using thermal oxide SiO$_2$ as a dielectrical isolation layer, SOI Hall sensors without pn junction isolation have been fabricated on Si/SiO$_2$/Si structures. The SOI structure was formed by SDB (Si- wafer direct bonding) technology. The Hall voltage and the sensitivity of Si Hall devices implemented on the SDB SOI structure show good linearity with respect to the appled magnetic flux density and supplied current. The product sensitivity of the SDB SOI Hall device is average 600V/V.T. In the trmperature range of 25 to 300$^{\circ}C$, the shifts of TCO(Temperature Coefficient of the Offset Voltage) and TCS(Temperature Coefficient of the Product Sensitivity) are less than ${\pm}$ 6.7x10$\^$-3/ C and ${\pm}$8.2x10$\^$04/$^{\circ}C$, respectively. These results indicate that the SDB SOI structure has potential for the development of Hall sensors with a high-sensitivity and high-temperature operation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.35-38
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• 2000

In this study, the rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.l8um semiconductor device. Through reverse moat pattern process, reduced moat density at high moat density, STI CMP process with low selectivity could be to fit polish uniformity between low moat density and high moat density. Because this reason, in-situ motor current end point detection method is not fit to the current EPD technology with the reverse moat pattern. But we use HSS without reverse moat pattern on STI CMP and take end point current sensing signal.[1] To analyze sensing signal and test extracted signal, we can to adjust wafer difference within $110{\AA}$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.13-16
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• 1998

An anomalous current characteristics which show the superposition of a low current level and high current level at the subthreshold region when SONOSFETs are in memory states were investigated. We have assumed this phenomena were resulted from the effect of parasitic transistors by LOCOS isolation and were modeled to a parallel equivalent circuit of one memory transistor and two parasitic transistors. Theoretical curves are well fitted in measured log I$_{D}$-V$_{G}$ curves independent of channel width of memory devices. The difference between low current level and high current level is apparently decreased with decrease of channel width of devices because parasitic devices dominantly contribute to the current conduction with decrease of channel width of memory devices. As a result, we concluded that the LOCOS isolation has to selectively adopt in the design of process for charge-trap type NVSM.VSM.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.838-843
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• 2002

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The reverse moat etch process has been used for the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process with conventional low selectivity slurries. Thus, the process became more complex, and the defects were seriously increased. In this paper, we studied the direct STI-CMP process without reverse moat etch step using high selectivity slurry(HSS). As our experimental results show, it was possible to achieve a global planarization without the complicated reverse moat process, the STI-CMP process could be dramatically simplified, and the defect level was reduced. Therefore the throughput, yield, and stability in the ULSI semiconductor device fabrication could be greatly improved.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.189-192
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• 2001

Recently, STI process is getting attention as a necessary technology for making high density of semiconductor by devices isolation method. However, it does have various problems caused by CMP nprocess, such as torn oxide defects, nitride residues on oxide, damages of si active region, contaminations due to post-CMP cleaning, difficulty of accurate end point detection in CMP process, etc. In this work, the various defects induced by CMP process was introduced and the above mentioned problems of CMP process was examined in detail. Finally, the guideline of future CMP process was presented to reduce the effects of these defects.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2003.11a
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• pp.919-922
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• 2003

The correlation between noise and vibration by a heavy-weight floor impact was studied. The triggering technique was used for increasing the reliability and stability to measure the level of sound pressure, sound intensity and vibration acceleration. The simple finite element and rigid body analysis method were suggested to calculate the natural frequencies of the multi-layer floor system. The result show that the isolation material adapted to reduce the light-weight floor impact noise, causing the natural frequency lower, make resonance with dominant driving frequency, and increase the noise level very sharply. Therefore the noise level Peak in the region of low frequency, below 63Hz, would be related with the natural frequencies of the floor system.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2003.05a
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• pp.191-195
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• 2003

충격음 저감재의 동탄성계수와 감쇠계수는 차단성능을 평가하는데 있어 중요한 물성치가 된다. 저감재의 동탄성계수는 뜬바닥구조의 고유진동수를 결정짓게 되며, 저감재의 동탄성계수가 높을수록, 즉 고유진동수가 높아짐에 따라 실험실 경량충격음레벨 저감량은 지수함수적으로 감소됨을 실험을 통해 알 수 있다. 또한, 저감재를 포함한 뜬바닥구조를 1자유도 진동계로 가정한 이론값과 실험실 경량충격음레벨 저감량의 결과가 비교적 잘 일치하는 것으로 나타났으며, 이 때 감쇠계수의 영향은 반드시 고려되어야 한다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.189-192
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• 2001

Recently, STI process is getting attention as a necessary technology for making high density of semiconductor by devices isolation method. However, it does have various problems caused by CMP process, such as torn oxide defects, nitride residues on oxide, damages of si active region, contaminations due to post-CMP cleaning, difficulty of accurate end point detection in CMP process, etc. In this work, the various defects induced by CMP process was introduced and the above mentioned Problems of CMP process was examined in detail. Finally, the guideline of future CMP process was presented to reduce the effects of these defects.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.162-164
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• 2004

Nanocrystalline silicon(nc-Si) thin films on the silicon substrates have been prepared by pulsed laser deposition(PLD). The optical and structural properties of films have been investigated depending on deposition temperature, annealing, and oxidation process. When the deposition temperature increased, photoluminescence(PL) intensity abruptly decreased and peaks showed red shift. Annealing process could reduce the number of defect centers. Oxidation had a considerable effect upon the formation and isolation of the nanocrystals. These results indicate that the formation mechanism of Si nanocrystals grown by PLD can be explained by three steps of growth, passivating defect centers, and isolation, sequentially.

• Proceedings of the Korean Society of Crop Science Conference
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• 2006.04a
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• pp.606-607
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• 2006