• 제목/요약/키워드: Is-Spice

검색결과 478건 처리시간 0.029초

Rail-to-Rail 입력단과 출력단을 갖는 3 V CMOS 연산증폭기의 최적 설계에 관한 연구 (A Study on the Optimum Design for 3 V CMOS Operational Amplifier with Rail-to-Rail Input Stage and Output Stage)

  • 박용희;황상준;성만영;김성진
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1995년도 하계학술대회 논문집 C
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    • pp.1120-1122
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    • 1995
  • This paper presents a 2-stage, simple, power-efficient 3V CMOS operational amplifier and its equation based design optimization. Because of its simple structure, it is very suitable as a VLSI library cell in analog/digital mixed-mode systems. The op-amp, which contains a constant-$g_m$ rail-to-rail input stage and a simple feedforward class-AB rail-to-rail output stage, is analyzed and the results are presented in the form of design equations and procedures, which provide an insight into the trade-offs among performance requirements. The results of SPICE simulations are shown to agree very welt with the use of design equations.

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A New AMOLED Pixel Circuit Employing a-Si:H TFTs for High Aperture Ratio

  • Shin, Hee-Sun;Lee, Jae-Hoon;Jung, Sang-Hoon;Kim, Chang-Yeon;Han, Min-Koo
    • Journal of Information Display
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    • 제6권2호
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    • pp.12-15
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    • 2005
  • We propose a new pixel design for active matrix organic light emitting diode (AM-OLED) displays using hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs). The pixel circuit is composed of five TFTs and one capacitor, and employs only one additional control signal line. It is verified by SPICE simulation results that the proposed pixel compensates the threshold voltage shift of the a-Si:H TFTs and OLED.

OTA를 이용한 단전원 구동 펄스폭 변조(Pulse Width Modulation) 회로 설계 (Design of PWM(Pulse Width Modulation) Circuit Using OTA with a single-voltage supply)

  • 박선웅;김희준;송재훈;이은진
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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    • pp.2843-2846
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    • 2003
  • This paper proposes a PWM(Pulse Width Modulation) circuit using CMOS OTA with a single-voltage supply. The OTA employed has an input stage which consists of a pair of two MOSFETs operating in plural operation regions. The MOSFETs work complemetarily and realize a rail-to-rail input range. The input stage requires no matching of an n-channel type input circuit and a p-channel type input circuit unlike conventional rail-to-rail input stages because the input stage is realized by single channel type MOSFETs. In order to confirm the validity of the proposed circuit, it is simulated by H-SPICE program. Futhermore, the proposed circuit will be integrated on chip using 0.35 $\mu\textrm{m}$ CMOS technology.

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자기조정 이중구동 경로를 가진 새로운 저전력 CMOS 버퍼 ((A New CMOS Buffer for Low Power with Self-Controlled Dual Driving Path))

  • 배효관;류범선;조태원
    • 전자공학회논문지SC
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    • 제39권2호
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    • pp.140-145
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    • 2002
  • 본 논문은 단락회로 전류를 없애기 위한 CMOS 버퍼회로에 대한 것이다. 최종 구동소자는 풀-업 PMOS와 풀-다운 NMOS로 구성하고 이를 구동하기 위해 두가지 경로를 입력신호로 선택되도록 하였다. 이러한 기법으로 최종 구동회로가 짧은 시간동안 tri-state가 되어 단락회로 전류를 차단하였다. 모의 실험결과 전원전압 3.3V에서 전력-지연 곱을 기존의 Tapered 버퍼[1]와 비교하여 약 42% 줄일 수 있었다

디커플링 방법을 이용한 RC-Coupled 배선의 해석적 지연시간 예측 모델 (An Analytical Switching-Dependent Timing Model for Multi-Coupled VLSI Interconnect lines)

  • 김현식;어영선;심종인
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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    • pp.439-442
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    • 2004
  • Timing delays due to VLSI circuit interconnects strongly depend on neighbor line switching patterns as well as input transition time. Considering both the input transition and input switching pattern, a new analytical timing delay model is developed by using the decoupling technique of transfer multi-coupled lines into an effective single line. The analytical timing delay model can determine the timing delay of multi-coupled lines accurately as well as rapidly. It is verified by using DSM-Technology ($0.1{\mu}m$ /low-k copper-based process) that the model has excellent agreement with the results of SPICE simulation.

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자성반도체의 가변 히스테리시스 특성 모델링 회로 (The variable hysteresis modeling circuit for spintronic device)

  • 황원석;조충현;김범수;이갑용;이창우;김동명;민경식;김대정
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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    • pp.447-450
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    • 2004
  • The modeling circuit becomes more important in developing various magnetic devices regarding the fact that the competitive architecture and circuitry should be developed simultaneously. In this paper, we introduce a modeling circuit for hysteresis characteristic of a magnetic device, which is a major characteristic in the spin dependent magnetic material. This transistor-level model is conspicuous in that it can be usefully embodied in real circuits rather than conventional SPICE models are only for simulations.

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Investigation of a Method for RF Circuits Analysis Based on Electromagnetic Topology

  • Park, Yoon-Mi;Chung, Young-Seek;Cheon, Chang-Yul;Jung, Hyun-Kyo
    • Journal of Electrical Engineering and Technology
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    • 제4권3호
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    • pp.396-400
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    • 2009
  • In this paper, electromagnetic topology (EMT) was used to analyze the electromagnetic compatibility (EMC) of RF circuits including passive and active components. It is difficult to obtain usable results for problems relating to electromagnetic coupling in complex systems when using conventional numerical or experimental methods. Thus it is necessary to find a new methodology for analyzing EMC problems in complicated electromagnetic environments. In order to consider the nonlinear characteristics of active components, a SPICE diode model was used. A power detector circuit and the receiver circuit of a radio control (RC) car were analyzed and experimented in order to verify the validity of this method.

직접회로용 BJT의 베이스 Gummel Number 해석 방법에 관한 연구 (A Study on the Method of the Analysis of the Base Gummel Number of the BJT for Integrated Circuits)

  • 이은구;김철성
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제52권2호
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    • pp.74-79
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    • 2003
  • The method of the analysis of the base Gummel number of the BJT(Bipolar Junction Transistor) for integrated circuits based upon the semiconductor physics is proposed and the method of calculating the doping profile of the base region using process conditions is presented. The transistor saturation current obtained from the proposed method of NPN BJT using 20V and 30V process shows an averaged relative error of 6.7% compared with the measured data and the transistor saturation current of PNP BJT shows an averaged relative error of 9.2% compared with the measured data

AC PDP 에 효율적인 전원시스템의 설계 (The design of efficient Power system for AC PDP)

  • 박현욱;안성훈;강필순;천창근;김철우
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2003년도 춘계전력전자학술대회 논문집(1)
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    • pp.121-124
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    • 2003
  • In this paper, a novel PFC AC / DC converter is presented to be appropriate for AC PDP's power driving system. The conventional PFC AC / DC converter has independent power stages and controllers for their switching respectively, which should have increased price, size on manufacturing and decreased its efficiency as well. So this advanced Single-Stage Power Factor Corrector is presented and verified through spice simulation.

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0.18μm NMOS 캐스코드 전류원 구조의 2.4GHz 콜피츠 전압제어발진기 설계 및 제작 (A Design and Fabrication of a 0.18μm CMOS Colpitts Type Voltage Controlled Oscillator with a Cascode Current Source)

  • 김종범;유정호;최혁산;황인갑
    • 전기학회논문지
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    • 제59권12호
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    • pp.2273-2277
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    • 2010
  • In this paper a 2.4GHz CMOS colpitts type microwave oscillator was designed and fabricated using H-spice and Cadence Spetre. There are 140MHz difference between the oscillation frequency and the resonance frequency of a tank circuit of the designed oscillator. The difference is seemed to be due to the parasitic component of the transistor. The inductors used in this design are the spiral inductors proposed in other papers. Cascode current source was used as a bias circuit of a oscillator and the output transistor of the current source is used as the oscillation transistor. A common drain buffer amplifier was used at the output of the oscillator. The measured oscillation frequency and output power of the oscillator are 2.173GHz and -5.53dBm.