• 대한전자공학회논문지SD
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• 제48권3호
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• pp.1-6
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• 2011

N-channel 산화물 박막 트랜지스터(Thin Film Transistor, 이하 TFT)만을 이용한 저소비전력 inverter, NAND, NOR의 논리 게이트 회로를 제안한다. 제안된 회로는 asymmetric feed-through와 bootstrapping을 이용해서 pull-up, pull-down 스위치가 동시에 켜지지 않도록 설계하였다. 그 결과로 출력신호 전압 범위가 입력신호 전압과 동일하고 정전류가 흐르지 않는다. 인버터는 5 개의 TFT와 2 개의 capacitor로, NAND 및 NOR 게이트는 각각 10 개의 TFT와 4 개의 capacitor로 구성된다. 산화물 TFT 모델을 사용하여 SPICE 시뮬레이션을 수행하여 제안된 회로의 동작을 성공적으로 검증하였다.

• 전자공학회논문지D
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• 제35D권6호
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• pp.28-36
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• 1998

낮은 전압에서 고속으로 동작이 가능한 고속 비반전 SOI 버퍼 회로를 제안하였다. 제안된 버퍼 회로는 효율적으로 연결된 보조 MOS 트랜지스터를 경유하여 바디 전압이 동적으로 제어된다. 소자 시뮬레이션을 수행하여 바디가 보조 MOS 트랜지스터로 제어되는 MOS 소자의 전류 구동능력을 보이고 기존의 다른 방식과 비교하였다. SPICE를 이용한 회로 시뮬레이션을 통하여 제안된 버퍼 회로의 지연시간 특성을 조사하고 같은 사양을 가진 기존의 SOI CMOS 버퍼 회로와 비교하였다. 같은 면적을 기준으로 하여 제안된 버퍼회로는 기존의 버퍼 회로에 비해 1.2 V의 동작전압과 2 pF의 부하용량에 대하여 약 36% 지연 시간 단축을 보였다.

• 한국식품조리과학회지
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• 제20권5호
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• pp.489-497
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• 2004

The purpose of this study was to investigate the characteristics of beef jerky with prepared various spices. The spices added included green tea, rosemary, clove, thyme, and parsley. According to the analysis of general ingredients, the moisture content was higher in the spice-added samples than in the control jerky, and the crude protein content was higher in green tea- and parsley-added samples. According to the mineral analysis, the most prevalent mineral was Na, followed by K, P, Mg, and Ca, with the contents of Mn and Cu being the least prevalent. Ca and Fe contents werehigher in green tea-added jerky than in samples prepared with other spices. High levels of leucine and lysine were seen amongst different essential amino acids. Total amino acids were within the control jerky containing the most abundant essential amino acids, followed by green tea- and parsley-added jerky. Measurements of texture, hardness and springiness in the spice-added samples appeared to be higher than in the control. Bitterness was higher in clove-addedsamples than in samples prepared with other spices. The evaluation of sensory properties showed that color is higher in green tea-, rosemary- and clove-added samples and that taste was best in green tea-added jerky, followed by parsley-added jerky. Overall quality was high in green tea- and parsley-added samples.

• 동아시아식생활학회지
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• 제6권3호
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• pp.307-316
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• 1996

This study was carried out as part of a basic works to improve the native chicken uses. The mechanical test on the native chicken boiled plain broth and the sensory test was surveyed the preference of three kinds of chickens(native chicken, whangchu, broiler) prepared with six different cooking methods-chicken boiled plain, chicken broiled in microwave, stewed chicken, chicken fried with spice, chicken cutlet, chicken curry using 120 Yeungnam University students and graduate students as the panel. The results were as follows; The panels preferred the viscosity of chicken boiled plain broth for two hous. The viscosity of chicken boiled plain broth for two hous with the spindle at 5, r.p.m. of 20.50.100 was 8.6, 13.6, 9.9 respectively, and salt concentration was 0.40wt%. In the wensory test by cooking mehtods, the results of preference are in the following order-chicken curry, chicken cutlet, chicken fried with spice, stewed chicken, chicken boiled plain and chicken broiled in microwave. The most preferred cooking method of the native chicken, whangchu and broiler is chicken boiled plain, broiled in microwave and stewed chicken resectively. They preferred the native chicken in texture and taste. But in color, aroma and appearence among the sensory characteristics, whangchuwas preferred by the panels.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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• pp.75-78
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• 1998

The SONOSFET Shows low operation voltage, high cell density, anti good endurance due to modified Fowler-Nordheim tunneling as memory charge injection method. In this paper, therefore, the NOR-type Flash EEPROM composed of SONOSFET, which has fast lead operation speed and Random Access characteristics, is proposed. An 8${\times}$8 bit NOR-type SONOSFET Flash EEPROM had been designed and its electrical characteristics were verified. Read/Write/Erase operations of it were verified with the spice parameters of SONOSFETs which had Oxide-Nitride-Oxide thickness of 65${\AA}$-165${\AA}$-35${\AA}$ and that of scaled down as 33${\AA}$-53${\AA}$-22${\AA}$, respectively. When the memory window of the scaled-down SONOSFET with 8V operation was similar to that of the SONOSFET with 13V operation, the Read operation delay times of the scaled-down SONOSFET were 25.4ns at erase state and 32.6ns at program state, respectively, and those of the SONOSFET were 23.5ns at erase state and 28.2ns at program state, respectively.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 추계학술대회 논문집
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• pp.463-466
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• 2000

According to the development of the semiconductor micro device technology, IC chip trends the high integrated, low power tendency. Nowadays, it can be showed the tendency of single chip in system level. But in the system level, IC operates by multi power supply voltages. So, semiconductor process is necessary for these multi power operation. Therefore, in this paper, dual gate high voltage device that operate by multi power supply of 5V and 20V fabricated in the 0.5${\mu}{\textrm}{m}$ CMOS process technology and its electrical characteristics were analyzed. The result showed that the characteristics of the 5V device almost met with the SPICE simulation, the SPICE parameters are the same as the single 5V device process. And the characteristics of 20V device showed that gate length 3um device was available without degradation. Its current was 520uA/um, 350uA/um for NMOS, PMOS and the breakdown voltages were 25V, 28V.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.811-814
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• 1998

This paper proposes a constant time-delay filter with low sensitivity, which can be used for hard-disk drive. The sensitivity of 2nd order lowpass filter by two kinds of method, one is based on lossy integrators and the other is lossy and lossless integrators is analyzed and designed. SPICE simulation shows fesibility of a filter by the proposed approach.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.549-550
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• 2008

This paper proposed and designed the modified flash analog-to-digital converter(ADC). The speed of new architecture is similar to conventional flash ADC but the die area consumption is much less due to reduce numbers of comparators. The circuits which are implemented in this paper is simulated with LT SPICE and layout with Electric tools of computer.

• 산학경영연구
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• 제13권
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• pp.179-193
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• 2000

소프트웨어 개발 프로세스의 품질관리 문제는 일반 제조상품과 달리 개발 공정과정과 제품자체의 복잡성 등으로 단순하지만은 않다. 최근 이러한 소프트웨어 프로세스 품질개선, 능력결정과 개발을 위한 국제 표준 ISO/IEC 15504가 완성되어 국내에도 적용되고 있으며, 이 결과는 국제적인 사례적용 보고서로 제출되어 등록되고 있다. 표준에 의한 소프트웨어 프로세스 심사의 기본은 해당 기본 프랙티스들의 수행여부와 수준을 확인함으로서 시작된다. 그리고 심사책임 및 신뢰성과 관련해서는 일반적으로 팀 단위로 구성된 심사원들이 프로세스 심사를 수행한다. 따라서 심사 팀의 구성과 프랙티스들의 중요도 선호가 프로세스 심사결과의 신뢰성과 객관성에 미치는 영향은 매우 크다. 본 연구에서는 실제 심사사례를 통해 나타난 해당 프로세스에 대한 기분 프팩티스들의 중요도와 심사결과를 비교해 소프트웨어 프로세스 심사사례를 분석한다. 연구 자료로는 ISO/IEC 15504 표준을 적용한 SPICE 실제 심사사례에 참여한 심사원 및 인터유 대상자들을 중심으로 수집한 설문자료를 이용하고, 이를 통계적 인자분석 방법을 통하여 결과를 도출한다. 향후 본 연구의 결과는 객관적이고 합리적인 심사 팀 구성을 위한 판단기준과 프랙티스 중요도 선호에 관한 정보를 제공함으로서 소프트웨어 프로세스 심사의 신뢰성과 효과성 향상에 기여할 수 있을 것이다.

• Journal of Information Technology Applications and Management
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• 제9권3호
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• pp.113-127
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• 2002

The effort for software process improvement is lately surging its interest though it does not satisfy both developer and receiver In terms of low productivity, quality, delay and increasing cost. According to current research, software process improvement contributes to improvement of productivity, its Duality, reduction of development time and cost, and the prediction of the time limit for delivery, which means software process improvement affects competitive advantage among developers. The latest research is whether the investment for information technology substantially had effect on improvement of productivity. That is, software process improvement and maturity of software industries has influence upon economic efficiency and as a result, it plays an important role in whole industries. This research is that how does software process improvement using CMM (Capability Maturity Model) and SPICE (Software Process Improvement and Capability dEtermination) have a effect on factors of software engineering, and how does it have influence upon competitive advantage among SI firms. For this research, reusability, customizability, participation, and review & inspection are set to independent variable and process flexibility and process predictability are set to mediate Variable. Finally, competitive advantage among SI firms Is set to dependent variable. The targets for survey are laborers who work for SI firms. The result of this research is as follows: 1 ) Reusability, Customizability and participation is not rejected but review and Inspection is rejected in process flexibility which has significant level 0.05. 2) Reusability, Customizability and participation is not rejected but review and inspection Is rejected in process predictability which has significant level 0.05. 3) Process flexibility is not rejected and process predictability Is rejected in the competitive advantage of 51 industries which has significant level 0.05