• Journal of the Korean Magnetics Society
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• v.5 no.5
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• pp.828-832
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• 1995

This paper describes the efficient design, analysis method and experimental verification of capacitor discharge impulse magnetizer system. A capacitor discharge magnetizer system is used to produce a high current impulse of short duration in this magnetizing fixture. The parasitic resistance and parasitic inductance of the capacitor discharge impulse magnetizer system have been estimated using known air-core test coil. Finite element analysis (using MAXWELL 2-D field simulator) and magnetizing circuit analysis (using SPICE) are also used as part of the design and analysis process of the capacitor discharge impulse magnetizer system. Application study for a magnetizing fixture design is shown. 8-pole magnetizing fixture has been designed and analyzed using finite element analysis. The fixture design for 8-pole magnet are presented along with the experimental results. The experimental results have been achieved using a high-voltage, high-energy capacitor discharge impulse magnetizer and 8-pole iron core fixtures (charging voltage : 2000[V], capacitor bank : 4000[$\mu\textrm{F}$]).

• Journal of the Semiconductor & Display Technology
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• v.16 no.3
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• pp.59-64
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• 2017

As the demand on displays increases, new thin-film transistors such as metal oxide transistor are continuously being invented. When designing a circuit consisting of such new transistors, a new transistor model based on proper charge transport mechanisms is needed for each of them. In this paper, a modeling framework which enables to choose charge transport mechanisms that are limited to certain operation regions and assemble them into a transistor model instead of making an integrated transistor model dedicated to each transistor. The framework consists of a graphic user interface to choose charge transport models and a current calculation part, which is also implemented in AIM-SPICE for circuit simulation.

• Korean Journal of Pharmacognosy
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• v.50 no.3
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• pp.159-164
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• 2019

Zanthoxylum Peel is widely used as a common spice for a variety of foods. In the orient, it has also been used as traditional agents for treating diseases such as indigestion. Recently, Zanthoxylum Peel has been reported to have anti-cancer activity, anti-microbial activity, and anti-inflammatory activity. Chemical components are known sanshool compounds and xanthoxylin. In this study, we were carried out to investigate the constituents of inhibiting a drug metabolizing enzyme CYP3A4 from Zanthoxylum Peel. CYP3A4 is known as an enzyme involved in drug metabolism as monooxygenase containing the heme. As a result of experiment, we found that bergapten ($IC_{50}=18.21{\mu}M$) and quercetin ($IC_{50}=17.27{\mu}M$) isolated from EtOAc extract of Zanthoxylum Peel showed remarkable CYP3A4-inhibiting activities. Structures of the isolated active compounds were established by chemical and spectroscopic means.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.459-465
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• 1987

This paper describes the circuit and the layout of the shift register which can be used for a scanner of image sensor. P-well concentration and threshold voltage for proper iperation are calculated on the basso of the fixed process and the layout design. The calculation procedure of maximum operation frequency is also carried out. It is ascertained by SPICE simulation that the shift register produces the outputn pulse without threshold voltage loss up to 13MHz.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.2
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• pp.347-354
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• 1987

Timing simulators are widely used nowadays for analyzing large-scale MOS digital circuits, which, however, have several limitations such as nonconvergence and/or in accuracy for circuits containing tightly coupled feedback elements or loops. This paper describes a new timing simulator which aims at solving these problems. The algorithm employed is based on the wave-form relaxation method, but exploits the signal flow along the feedback loops. Each of feedback loops is treated as one circuit block and then local iterations are performed to enhance the timing simulation. With these techniques, out simulator can analyze the MOS digital circuits with up to 5-20 times of the magnitude speed improvemnets as compared to SPICE2, while maintaining the accuracy.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.48-57
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• 2020

MCU used in applications such as wireless chargers and USB type-C require MTP memory with a small cell size and a small additional process mask. Conventional double poly EEPROM cells are small in size, but additional processing masks of about 3 to 5 sheets are required, and FN tunneling type single poly EEPROM cells have a large cell size. In this paper, a 110nm MTP cell using a vertical PIP capacitor is proposed. The erase operation of the proposed MTP cell uses FN tunneling between FG and EG, and the program operation uses CHEI injection method, which reduces the MTP cell size to 1.09㎛2 by sharing the PW of the MTP cell array. Meanwhile, MTP memory IP required for applications such as USB type-C needs to operate over a wide voltage range of 2.5V to 5.5V. However, the pumping current of the VPP charge pump is the lowest when the VCC voltage is the minimum 2.5V, while the ripple voltage is large when the VCC voltage is 5.5V. Therefore, in this paper, the VPP ripple voltage is reduced to within 0.19V through SPICE simulation because the pumping current is suppressed to 474.6㎂ even when VCC is increased by controlling the number of charge pumps turned on by using the VCC detector circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.15-23
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• 2009

Microprocessors, which need correct arithmetic operations, have been the subject of in-depth research in relation to soft errors. Of the existing microprocessor devices, the memory cell is the most vulnerable to soft errors. Moreover, when soft errors emerge in a memory cell, the processes and operations are greatly affected because the memory cell contains important information and instructions about the entire process or operation. Users do not realize that if soft errors go undetected, arithmetic operations and processes will have unexpected outcomes. In the field of architectural design, the tool that is commonly used to detect and correct soft errors is the error check and correction code. The Itanium, IBM PowerPC G5 microprocessors contain Hamming and Rasio codes in their level-2 cache. This research, however, focuses on huge server devices and does not consider power consumption. As the operating and threshold voltage is currently shrinking with the emergence of high-density and low-power embedded microprocessors, there is an urgent need to develop ECC (error check correction) circuits. In this study, the in-output data of the level-2 cache were analyzed using SimpleScalar-ARM, and a 32-bit H-matrix for the level-2 cache of an embedded microprocessor is proposed. From the point of view of power consumption, the proposed H-matrix can be implemented using a schematic editor of Cadence. Therefore, it is comparable to the modified Hamming code, which uses H-spice. The MiBench program and TSMC 0.18 um were used in this study for verification purposes.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.47-56
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• 1999

As the density of logic gates of VLSI chips has rapidly increased, more number of I/O pins has been required. This results in bigger package size and higher packager cost. The package cost is higher than the cost of bare chips for high I/O count VLSI chips. As the density of logic gates increases, the reduction method of the number of I/O pins for a given complexity of logic gates is required. In this paper, we propose the novel I/O interface circuit using CTR (Constant-Transition-Rate) code to reduce 50% of the number of I/O pins. The rising and falling edges of the symbol pulse of CTR codes contain 2-bit digital data, respectively. Since each symbol of the proposed CTR codes contains 4-bit digital data, the symbol rate can be reduced by the factor of 2 compared with the conventional I/O interface circuit. Also, the simultaneous switching noise(SSN) can be reduced because the transition rate is constant and the transition point of the symbols is widely distributed. The channel encoder is implemented only logic circuits and the circuit of the channel decoder is designed using the over-sampling method. The proper operation of the designed I/O interface circuit was verified using. HSPICE simulation with 0.6 m CMOS SPICE parameters. The simulation results indicate that the data transmission rate of the proposed circuit using 0.6 m CMOS technology is more than 200 Mbps/pin. We implemented the proposed circuit using Altera's FPGA and confimed the operation with the data transfer rate of 22.5 Mbps/pin.

• Journal of Bio-Environment Control
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• v.27 no.4
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• pp.356-362
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• 2018

Hot pepper is a kind of seasoning vegetables, which is a major item in the Korean vegetable market. Since the use of hot pepper is processed into pepper powder, which is a powder form of dried hot pepper, improvement of quality and productivity of dried hot pepper is important. Therefore, this experiment was conducted to suggest proper drying method by comparing the changes of hot pepper powder ingredients considering production cost according to the drying method. As a drying method, we used sun drying and heat drying which are widely used in practice. We also compared the productivity and quality of dried hot pepper by applying a dehumidifying drying method using a dehumidifier. Drying rate of hot pepper was highest of 85.1% at heat drying. Accordingly moisture content of hot pepper powder was lowest of 13.5% at heat drying. The American Spice Trade Association (ASTA) color value, which influenced the coloring of red pepper, showed higher in heat drying and dehumidified drying treatment than the sun drying treatment. The content of capsaicinoids was higher at sun drying treatment than that of at both heat drying and dehumidified drying treatments. The content of sugar was higher at heat drying and dehumidified drying treatment where drying time was relatively short than that of sun drying treatment. Also, there was no significant difference in sugar content between the two treatments. The production cost of dried hot pepper with dehumidified drying was 9.9% more efficient than heat drying. Through this study, it was found that heat and dehumidified drying method were effective in increasing sugar content and coloring of hot pepper powder. In order to improve the capsaicinoid content of red pepper, it is considered that appropriate drying temperature and drying time should be added in the process of heat drying and dehumidified drying.

• 전자공학회논문지 IE
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• v.49 no.1
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• pp.18-23
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• 2012

In this paper, a potable device application for DC-DC converter was designed for voltage protection circuit. Voltage protection circuit to offer the under voltage lock out and over voltage protection consists of a comparator and bais circuits were implemented using. XFAB 1um CMOS process, SPICE simulations was confirmed through the characteristics. Simulation results, under voltage lock out input voltage is 4.8 V higher when the turn-on and, 4.2 V less when turn-off. When the input voltage is low voltage is applied can be used to prevent malfunction of the circuit. Over voltage protection is 3.8 V reference voltage when the output voltage caused by blocking circuit prevents device destruction can be used to improve the stability and reliability. The virtual control circuits of the DC-DC converter connected. According to the results of the abnormal voltage, voltage protection circuit behavior was confirmed. The proposed voltage protection circuit of the DC-DC converter cell is useful are considered.