• Journal of the Korea Academia-Industrial cooperation Society
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• v.4 no.4
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• pp.346-351
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• 2003

In spite of the size and complexity of software becomes large and complicated, the demand of rapid development, cost reduction, good productivity and good quality software is increasing in these days. Many methods were proposed for efficient software development such as various Case tools. Metrics, Process improvement model (CMM, SPICE, ISO9000) and etc. However, most of them we useful to manage the whole projects rather than an individual programming. In this paper, we introduced a system for quality assessment and complexity metrics for Java programs to assess the individual programmer's quality rather than team's quality. This system shows not only the metrics value for quality assessment but also the source code and the soucture of classes simultaneously.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.251-265
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• 2001

As the device scaling proceeds, the operating voltage(VDD) of giga-bit DRAMs is expected to be reduced to 1.5V or down, fir improving the device reliability and reducing the power dissipation. Therefore the low-voltage circuit design techniques are required to implement giga-bit DRAMs. In this work, state-of-art low-voltage DRAM circuit techniques are reviewed, and four kinds of low-voltage circuit design techniques are newly proposed for giga-bit DRAMs. Measurement results of test chips and SPICE simulation results are presented for the newly proposed circuit design techniques, which include a hierarchical negative-voltage word-line driver with reduced subthreshold leakage current, a two-phase VBB(Back-Bias Voltage) generator, a two-phase VPP(Boosted Voltage) generator and a bandgap reference voltage generator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.302-312
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• 2001

As the data transfer rate between chips gets higher, both crosstalk and SSN (Simultaneous Switching Noise) deteriorate seriously the performance of a system. The proposed interface scheme uses P-CTR and N-CTR(Positive/Negative Constant Transition Rate) which encodes data at both falling and rising edges, where the transition directions of N-CTR and P-CTR are opposite. And the proposed bus system places two P-CTR drivers and two N-CTR drivers alternatively. In the proposed P/N-CTR interface scheme, the signals of neighboring interconnection lines at both sides of a bus will not switch simultaneously in the same direction, which leads to reduction in the maximum crosstalk and SSN compared to conventional interfaces. For verification of noise reduction of the proposed interface scheme, the scheme is applied to several kinds of bit-wide buses with various interconnection structures, and HSPICE simulation was performed with 0.35 ${\mu}{\textrm}{m}$ SPICE parameters. The simulation results show that in the 32-bit or less wide bus, the maximum SSN and crosstalk are reduced to at least 26.78% and 50%, respectively in comparison with the conventional interface scheme.

• Food Science of Animal Resources
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• v.44 no.3
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• pp.635-650
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• 2024

In this study, we analyzed the physicochemical and sensory properties of black goat jerky marinated with various spices (non-spice, control; rosemary, RO; basil, BA; ginger, GI; turmeric, TU; and garlic, GA). The physicochemical properties of black goat jerky analyzed were pH, water holding capacity, color, cooking yield, shear force, and fatty acid composition. The sensory characteristics were analyzed through the aroma profile (electronic nose), taste profile (electronic tongue), and sensory evaluation. The pH and water holding capacity of the GI showed higher values than the other samples. GI and GA showed similar values of CIE L^* and CIE a^* to that of the control. The shear force of the GI and TU was significantly lower than that of other samples (p<0.05). Regarding fatty acid composition, GI showed high unsaturated and low saturated fatty acid contents compared with that of the other samples except for RO (p<0.05). In the aroma profile, the peak area of hexanal, which is responsible for a faintly rancid odor, was lower in all treatment groups than in the control. In the taste profile, the umami of spice samples was higher than that of the control, and among the samples, GI had the highest score. In the sensory evaluation, the GI sample showed significantly higher scores than the control in terms of flavor, aroma, goaty flavor, and overall acceptability (p<0.05). Therefore, marinating black goat jerky with ginger powder enhanced the overall flavor and reduced the goat odor.

• Proceedings of the KIEE Conference
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• 1996.07a
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• pp.537-539
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• 1996

In this paper, a design method of the phase shift ZVS-PWM converter is proposed to minimize the volume and increase the efficiency. The trade-offs of switching frequency, efficiency vs volume and ZVS range vs efficiency is also presented. The simulation of the designed converter is performed using the P-SPICE in which a phase-shift controller is proposed. For minimization of the converter volume, switching frequency is selected 100kHz, a simple drive circuit and single auxiliary supply are applied. In consideration of efficiency and load condition, ZVS range is decided from 50% to full load. A 28V, 1Kwatt prototype converter, of which the switch is MOSFET is made, verified the performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.7
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• pp.1716-1725
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• 1996

In this paper, the huffman decoder which is a part of the decoder in JPEG standard format is designed by using a new Ternary CAM. First, the 256 word * 16 bit-size new bit-word all parallel Ternary CAM system is designed and verified using SPICE and CADENCE Verilog-XL, and then the verified novel Ternary CAM is applied to the new huffman decoder architecture of JPEG. So the performnce of the designed CAM cell and it's block is verified. The new Ternary CAM has various applications because it has search data mask and storing data mask function, which enable bit-wise search and don't care state storing. When the CAM is used for huffman look-up table in huffman decoder, the CAM is partitioned according to the decoding symbol frequency. The scheme of partitioning CAM for huffman table overcomes the drawbacks of all-parallel CAM with much power and load. So operation speed and power consumption are improved.

• The Journal of the Acoustical Society of Korea
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• v.18 no.3E
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• pp.44-48
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• 1999

The CMOS four-quadrant analog multiplier for low-voltage low-power applications are presented in this thesis. The circuit approach is based on the characteristic of the LV (Low-Voltage) composite transistor which is one of the useful analog building block. SPICE simulations are carried out to examine the performances of the designed multiplier. Simulation results are obtained by 0.6㎛ CMOS parameters with 2V power supply. The basic configuration of the multiplier is the CMOS Gilbert cell with two LV composite transistors. The linear input range of the multiplier is over ±0.4V with a linearity error of less than 1.3%. The measured -3dB bandwidth is 288MHz and the power dissipation is 255 ㎼.

• Proceedings of the KIEE Conference
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• 2006.10d
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• pp.244-246
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• 2006

Softwares in railway system are being used in the area of railway control system, directly associated to safety. Because the instinct characteristic of Software is uncertainty, Software development without safety insurance is very hazardous situation. In order to derive safety certification process in the railway system, certification and approval processes in the nuclear, aviation, and military area are studied. Software quality should be improved by two aspects : one is product aspect, another is process aspect. GS(Good Software) and ES(Excellent Software) certification can be exemplified in a product aspect approach. In those process certification, CMMI (Capability Maturity Model Integration) or SPICE (Software Process Improvement and Capability dEtermination : ISO/IEC15504) is being used as models for assessing process maturity of organization. Following the studies, safety management procedure in the railway system is suggested.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.310-312
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• 1994

A partial shunt regulator (PSR) which is the power regulator of KOREASAT is modeled. The modeling of the PSR consist of solar array, power circuit, controller. and load models. To realize simple structure. a voltage source of the PSR controller is used the output voltage of the PSR. The model of the PSR has very complex structure with two additional coupled feedback loops. The complex model is simplified to a simple meaningful model with only main feedback control loop. The proposed model is compared to a PSR model with DC voltage source at the PSR controller. The proposed PSR model is verified by comparing the model with SPICE simulation for small signal analysis.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.1
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• pp.10-16
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• 2016

In this paper, a design for a fully digital voltage sensor using a 32-nm fin-type field-effect transistor (FinFET) is presented. A new characteristic of the double gate p-type FinFET (p-FinFET) is examined and proven appropriate for sensing voltage variations. On the basis of this characteristic, a novel technique for designing low-power voltage-to-time converters is presented. Then, we develop a digital voltage sensor with a voltage range of 0.7 to 1.1V at a 50-mV resolution. The performance of the proposed sensor is evaluated under a range of voltages and process variations using Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, and the sensor is proven capable of operating under ultra-low power consumption, high linearity, and fairly high-frequency conditions (i.e., 100 MHz).