• Title/Summary/Keyword: Is-Spice

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Low Power Digital Logic Gate Circuits Based on N-Channel Oxide TFTs (N-Channel 산화물 TFT 기반의 저소비전력 논리 게이트 회로)

  • Ren, Tao;Park, Kee-Chan;Oh, Hwan-Sool
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.3
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    • pp.1-6
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    • 2011
  • Low-power logic gates, i.e. inverter, NAND, and NOR, are proposed employing only n-channel oxide thin film transistors (TFTs). The proposed circuits were designed to prevent the pull-up and pull-down switches from being turned on simultaneously by using asymmetric feed-through and bootstrapping, thereby exhibited same output voltage swing as the input signal and no static current. The inverter is composed of 5 TFTs and 2 capacitors. The NAND and the NOR gates consist of 10 TFTs and 4 capacitors respectively. The operations of the logic gates were confirmed successfully by SPICE simulation using oxide TFT model.

High Speed Non-Inverting SOI Buffer Circuit by Adopting Dynamic Threshold Control (동적 문턱전압 제어 기법을 이용한 고속 비반전 SOI 버퍼 회로)

  • 이종호;박영준
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.6
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    • pp.28-36
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    • 1998
  • We have proposed a new non-inverting SOI buffer circuit for the high speed operation at low supply voltage. The body biases of main MOS devices in the proposed circuit are controlled dynamically via subsidiary MOS device connected efficiently to the body terminal. We showed current derivability of the body controlled devices obtained by device simulation and compared with that of conventional SOI devices. Delay time characteristics of the buffer circuit were analyzed by SPICE simulation and compared with those of conventional SOI CMOS buffer circuits. Delay time reduction of the SOI buffer over conventional SOI CMOS buffer with same area is about 36 % at $V_{S}$=1.2 V and $C_{L}$=2 pF. pF.

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The Quality Characteristics of Beef Jerky prepared with Various Spices (향신료를 첨가한 육포의 이화학적ㆍ관능적 품질 특성)

  • Lee Sun-Iu;Park Geum-Soon
    • Korean journal of food and cookery science
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    • v.20 no.5
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    • pp.489-497
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    • 2004
  • The purpose of this study was to investigate the characteristics of beef jerky with prepared various spices. The spices added included green tea, rosemary, clove, thyme, and parsley. According to the analysis of general ingredients, the moisture content was higher in the spice-added samples than in the control jerky, and the crude protein content was higher in green tea- and parsley-added samples. According to the mineral analysis, the most prevalent mineral was Na, followed by K, P, Mg, and Ca, with the contents of Mn and Cu being the least prevalent. Ca and Fe contents werehigher in green tea-added jerky than in samples prepared with other spices. High levels of leucine and lysine were seen amongst different essential amino acids. Total amino acids were within the control jerky containing the most abundant essential amino acids, followed by green tea- and parsley-added jerky. Measurements of texture, hardness and springiness in the spice-added samples appeared to be higher than in the control. Bitterness was higher in clove-addedsamples than in samples prepared with other spices. The evaluation of sensory properties showed that color is higher in green tea-, rosemary- and clove-added samples and that taste was best in green tea-added jerky, followed by parsley-added jerky. Overall quality was high in green tea- and parsley-added samples.

A Study for the Mechanical and Sensory Characteristics of Chickens by Cooking Methods -For the Focus on Native Chicken- (조리 방법에 따른 닭의 기계적.관능적 특성 -토종닭을 중심으로-)

  • 한재숙;한경필;김정숙;김미향
    • Journal of the East Asian Society of Dietary Life
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    • v.6 no.3
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    • pp.307-316
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    • 1996
  • This study was carried out as part of a basic works to improve the native chicken uses. The mechanical test on the native chicken boiled plain broth and the sensory test was surveyed the preference of three kinds of chickens(native chicken, whangchu, broiler) prepared with six different cooking methods-chicken boiled plain, chicken broiled in microwave, stewed chicken, chicken fried with spice, chicken cutlet, chicken curry using 120 Yeungnam University students and graduate students as the panel. The results were as follows; The panels preferred the viscosity of chicken boiled plain broth for two hous. The viscosity of chicken boiled plain broth for two hous with the spindle at 5, r.p.m. of 20.50.100 was 8.6, 13.6, 9.9 respectively, and salt concentration was 0.40wt%. In the wensory test by cooking mehtods, the results of preference are in the following order-chicken curry, chicken cutlet, chicken fried with spice, stewed chicken, chicken boiled plain and chicken broiled in microwave. The most preferred cooking method of the native chicken, whangchu and broiler is chicken boiled plain, broiled in microwave and stewed chicken resectively. They preferred the native chicken in texture and taste. But in color, aroma and appearence among the sensory characteristics, whangchuwas preferred by the panels.

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Scaled SONOSFET NOR Type Flash EEPROM (Scaled SONOSFET NOR형 Flash EEPROM)

  • 김주연;권준오;김병철;서황열
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1998.06a
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    • pp.75-78
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    • 1998
  • The SONOSFET Shows low operation voltage, high cell density, anti good endurance due to modified Fowler-Nordheim tunneling as memory charge injection method. In this paper, therefore, the NOR-type Flash EEPROM composed of SONOSFET, which has fast lead operation speed and Random Access characteristics, is proposed. An 8${\times}$8 bit NOR-type SONOSFET Flash EEPROM had been designed and its electrical characteristics were verified. Read/Write/Erase operations of it were verified with the spice parameters of SONOSFETs which had Oxide-Nitride-Oxide thickness of 65${\AA}$-165${\AA}$-35${\AA}$ and that of scaled down as 33${\AA}$-53${\AA}$-22${\AA}$, respectively. When the memory window of the scaled-down SONOSFET with 8V operation was similar to that of the SONOSFET with 13V operation, the Read operation delay times of the scaled-down SONOSFET were 25.4ns at erase state and 32.6ns at program state, respectively, and those of the SONOSFET were 23.5ns at erase state and 28.2ns at program state, respectively.

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A Study on the 0.5$\mu\textrm{m}$ Dual Gate High Voltage Process for Multi Operation Applications (Multi Operation을 위한 0.5$\mu\textrm{m}$Dual Gate 고전압 공정에 관한 연구)

  • 송한정;김진수;곽계달
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.11a
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    • pp.463-466
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    • 2000
  • According to the development of the semiconductor micro device technology, IC chip trends the high integrated, low power tendency. Nowadays, it can be showed the tendency of single chip in system level. But in the system level, IC operates by multi power supply voltages. So, semiconductor process is necessary for these multi power operation. Therefore, in this paper, dual gate high voltage device that operate by multi power supply of 5V and 20V fabricated in the 0.5${\mu}{\textrm}{m}$ CMOS process technology and its electrical characteristics were analyzed. The result showed that the characteristics of the 5V device almost met with the SPICE simulation, the SPICE parameters are the same as the single 5V device process. And the characteristics of 20V device showed that gate length 3um device was available without degradation. Its current was 520uA/um, 350uA/um for NMOS, PMOS and the breakdown voltages were 25V, 28V.

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A 2nd-order Lowpass Filter with Low Group-Delay Sensitivity (저 감도 지연특성을 갖는 2차 저역통과 필터)

  • 안정철;김춘수최석우윤창훈
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.811-814
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    • 1998
  • This paper proposes a constant time-delay filter with low sensitivity, which can be used for hard-disk drive. The sensitivity of 2nd order lowpass filter by two kinds of method, one is based on lossy integrators and the other is lossy and lossless integrators is analyzed and designed. SPICE simulation shows fesibility of a filter by the proposed approach.

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Implementation of Modified CMOS Flash AD Converter (수정된 CMOS 플래시 AD변환기 구현)

  • Kwon, Seung-Tag
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.549-550
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    • 2008
  • This paper proposed and designed the modified flash analog-to-digital converter(ADC). The speed of new architecture is similar to conventional flash ADC but the die area consumption is much less due to reduce numbers of comparators. The circuits which are implemented in this paper is simulated with LT SPICE and layout with Electric tools of computer.

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Base Practice Importance Analysis by Software Process Assessors' Characteristics (소프트웨어 프로세스 심사원 특성에 따른 기본 프랙티스의 중요도 분석)

  • Lee, Jong-Moo;Yoo, Young-Kwan;Kim, Gil-Jo;Chun, In-Geol
    • Korean Business Review
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    • v.13
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    • pp.179-193
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    • 2000
  • It is not simple to manage software quality, because software development process and product itself are very complex. Recently ISO/IEC 15504- international standard for software process improvement, capability determination and development - was completed and applied to many local trials, and their results are being reported as registered local trials. The first step of software process assessment is established by examining whether its base practices are performed and which level they are achieved. And as far as assessment responsibility and credibility are concerned, assessment is generally performed by team-based assessors. Therefore assessment team construction and its preference of practice importances have a great effect on the credibility and the objectivity of assessment. In this paper, we analyse a SPICE-based software process assessment trial by comparing base practice importances of assessed processes, which are expressed through a real assessment, with its final rating results. Survey data are collected from assessors and interviewees who were engaged in the SPICE trial that was performed by ISO/IEC 15504, and final data analysis are derived from the factor analysis method. It is convinced that the result of this paper is able to enhance the credibility of software process assessment by provisions of objective and rational criteria and preference information for assessment team construction and base practice importances in future.

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A Study on Effects of Software Process Improvement for Competitive Advantage (소프트웨어 프로세스 개선 노력이 국내 SI 업체의 경쟁우위에 미치는 영향에 관한 연구)

  • 김성희;이경아;이주헌
    • Journal of Information Technology Applications and Management
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    • v.9 no.3
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    • pp.113-127
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    • 2002
  • The effort for software process improvement is lately surging its interest though it does not satisfy both developer and receiver In terms of low productivity, quality, delay and increasing cost. According to current research, software process improvement contributes to improvement of productivity, its Duality, reduction of development time and cost, and the prediction of the time limit for delivery, which means software process improvement affects competitive advantage among developers. The latest research is whether the investment for information technology substantially had effect on improvement of productivity. That is, software process improvement and maturity of software industries has influence upon economic efficiency and as a result, it plays an important role in whole industries. This research is that how does software process improvement using CMM (Capability Maturity Model) and SPICE (Software Process Improvement and Capability dEtermination) have a effect on factors of software engineering, and how does it have influence upon competitive advantage among SI firms. For this research, reusability, customizability, participation, and review & inspection are set to independent variable and process flexibility and process predictability are set to mediate Variable. Finally, competitive advantage among SI firms Is set to dependent variable. The targets for survey are laborers who work for SI firms. The result of this research is as follows: 1 ) Reusability, Customizability and participation is not rejected but review and Inspection is rejected in process flexibility which has significant level 0.05. 2) Reusability, Customizability and participation is not rejected but review and inspection Is rejected in process predictability which has significant level 0.05. 3) Process flexibility is not rejected and process predictability Is rejected in the competitive advantage of 51 industries which has significant level 0.05

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