• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.5A
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• pp.311-316
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• 2012

In this paper, a bit-mapping scheme is proposed for partial Chase combining in LDPC-coded systems. Contrary to the previously known bit mapping that assigns the information bits to more reliable channels, the proposed mapping assigns the codeword bits of irregular LDPC codes to distinct Gaussian channels by considering the characteristics of LDPC codes and channels. The recursion equation for partial Chase combining is derived by using the density evolution technique, based on it, the best bit mapping among the various bit-mapping schemes is derived, and the validity of them is confirmed through simulation.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.134-134
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• 2004

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.4
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• pp.278-285
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• 2011

This paper makes an analysis of the encoding structure and the decoding algorithm proposed by the DVB-S2 specification. The methods of implementing the LDPC decoder are fully serial decoder, the partially parallel decoder and the fully parallel decoder. The partial parallel scheme is the efficient selection to achieve appropriate trade-offs between hardware complexity and decoding speed. Therefore, this paper proposed an efficient memory structure for check node update block, bit node update block, and LLR memory.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.12
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• pp.1745-1747
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• 2016

In this paper, we propose a construction method of irregular quasi-cyclic low-density parity-check codes based on perfect difference families with various block sizes. The proposed codes have advantages in that they support various values with respect to code rate, length, and degree distribution. Also, this construction enables very short lengths which are usually difficult to be achieved by a random construction. We verify via simulations the error-correcting performance of the proposed codes.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.04a
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• pp.631-634
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• 2010

기존의 Quasi-Cyclic LDPC 부호는 하나의 기본행렬의 순환행렬을 부행렬로 사용하여 패리티 검사 행렬을 만든다. 본 논문에서는 무게가 서로 다른 두 개의 기본 행렬의 순환행렬들과 영행렬을 부행렬로 사용하고, 이 세 개의 부행렬들을 주어진 조건하에서 무작위로 조합하여 패리티 검사 행렬을 만드는 방법을 제안한다. 제안된 LDPC 부호는 girth가 6이상인 Irregular LDPC 부호이다.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.72-79
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• 2014

This paper presents a method for constructing a pipeline-aware quasi-cyclic irregular repeat accumulate low-density parity-check (PA-QC-IRA-LDPC) codes and efficient rate-1/2 (2016, 1008) PA-QC-IRA-LDPC decoder architecture. A novel pipeline scheduling method is proposed. The proposed methods efficiently reduce the critical path using pipeline without any bit error rate (BER) degradation. The proposed pipeline-aware LDPC decoder provides a significant improvement in terms of throughput, hardware efficiency, and energy efficiency. Synthesis and layout of the proposed architecture is performed using 90-nm CMOS standard cell technology. The proposed architecture shows more than 53% improvement of area efficiency and much better energy efficiency compared to the previously reported architectures.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.419-426
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• 2014

This paper proposes a high-throughput encoding process and encoder architecture for quasi-cyclic low-density parity-check codes in IEEE 802.11ac standard. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoding throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. In IEEE 802.11ac systems, the proposed encoder is rate compatible to support various code rates and codeword block lengths. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.118-124
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• 2008

For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.9
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• pp.817-825
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• 2013

The UHDTV system, which provides realistic service with ultra-high definite video and multi-channel audio, has been studied as a next generation broadcasting service. Since the conventional digital terrestrial transmission system is not capable to cover the increased transmission data rate of the UHDTV service, there are great necessity of researches about increase of data rate. Accordingly, the researches has been studied to increase the transmission data rate of the DVB-T2 system using dual-polarized MIMO technique and high order modulation. In order to optimize the MIMO DVB-T2 system where irregular LDPC codes are used, it is necessary to study the design of the bit mapper that matches the LDPC code and QAM symbols in MIMO channel. However, the research related to the design of the bit mapper has been limited to the SISO system. Therefore, this paper defines a new parameter that indicates the VND distribution of MIMO DVB-T2 system and performs the performance analysis according to the parameter which will be helpful for designing a MIMO bit mapper.