• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.291.2-291.2
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• 2016

3D semiconductor material of silicon that is used throughout the semiconductor industry currently faces a physical limitation of the development of semiconductor process technology. The research into the next generation of nano-semiconductor materials such as semiconductor properties superior to replace silicon in order to overcome the physical limitations, such as the 2-dimensional graphene material in 2D transition-metal dichalcogenide (TMD) has been researched. In particular, 2D TMD doping without severely damage of crystal structure is required different conventional methods such as ion implantation in 3D semiconductor device. Here, we study a p-type doping technique on tungsten diselenide (WSe2) for p-channel 2D transistors by adjusting the concentration of hydrochloric acid through Raman spectroscopy and electrical/optical measurements. Where the performance parameters of WSe2 - based electronic device can be properly designed or optimized. (on currents increasing and threshold voltage positive shift.) We expect that our p-doping method will make it possible to successfully integrate future layered semiconductor devices.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.421-424
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• 1998

In this paper are presented a newly proposed 3D monte carlo (MC) damage model for the dynamic simulation in order to more accurately and consistently predict the implant-induced point defect distributions of the various ions in crystalline silicon. This model was applied to phosphorus implants for the ULSI CMOS technology developement. In additon, a newly applied 3D-trajectory split method has been implemented into our model to reduce the statistical fluctuations of the implanted impurity and the defect profiles in the relatively large implanted area as compared to 1D or 2D simulations. Also, an empirical electronic energy loss model is proposed for phosphorus and silicon implants. The 3D formations of the amorphous region and the ultra-shallow junction around the implanted region could be predicted by using our model, TRICSI(Transport ions into crystal-silicon).

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.451-458
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• 2006

The Chair of Display Technology at the University of Stuttgart develops various technologies for active matrix applications. Last year we presented an LTPS active matrix process without the need for ion implantation. This process is compared to other AM processes and the technological demands for different applications are discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권6호
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• pp.662-667
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• 2013

The effect of fluorine ions, which can be reacted with boron in high-doped BPSG, is investigated on the contact sidewall wiggling profile in semiconductor process. In the semiconductor device, there are many contacts on $p^+/n^+$ source and drain region. However these types of wiggling profile is only observed at the $n^+$ contact region. As a result, we find that the type of plug implantation dopant can affect the sidewall wiggling profile of contact. By optimizing the proper fluorine gas flow rate, both the straight sidewall profile and the desired electrical characteristics can be obtained. In this paper, we propose a fundamental approach to improve the contact sidewall wiggling profile phenomena, which mostly appear in high-doped BPSG on next-generation DRAM products.

• 세라미스트
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• 제21권2호
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• pp.75-82
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• 2018

In the photovoltaics (PV) industry, there were many efforts to reduce the cost of production with high efficiency. The single most important cost factor in silicon technology is the wafer, accounting presently for ~35% of the module cost. it was already shown that the solar cell efficiency can be maintained up to the thickness range of $40-60{\mu}m$. The direct production of ultra-thin silicon wafer is very attractive and numerous different techniques, such as electrochemical process, ion implantation, and epitaxial growth, have been proposed and developed in many academic and industrial laboratories.

• Journal of Korean Vacuum Science & Technology
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• 제2권2호
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• pp.97-100
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• 1998

We have investigated the effects of crystalline activation on solid phase crystallization (SPC) of amorphous silicon (a-Si) thin films. Wet blasting and self ion implantation were employed as the activation treatments to induce macro or micro crystalline damages on deposited a-Si films. Low temperature and larger grain crystallization were obtained by the applied two-step activation. High degree of crystallinity was also observed on both furnace and rapid SPC. crystalline activations showed the promotion of nucleation on the activated regions and the retardation of growth in an amorphous matrix in SPC. The observed behavior of two-step SPC was strongly dependent on the applied activation and annealing processes. It was also found that the diversified effects by macro and micro activations on the SPC were virtually diminished as the annealing temperature increased.

• 한국진공학회지
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• 제7권s1호
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• pp.78-84
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• 1998

Niobium ions of 380 keV energy have been implanted at 300k in sapphire with a dose of $5\times10^{16}\textrm{ions/cm}^2$ and subsequently thermal annealed up to $1100^{\circ}C$ at reducing atmosphere. The behavior of the radiation damage produced by ion implantation followed by annealing is investigated using optical absorption technique and X-ray photoelectron spectroscopy(XPS). It is found that different defects annealed are dependent on the annealing temperature owing to different mechanisms which are proposed on the basis of the optical absorption measurement, and the implanted niobium in sapphire is in different local environments with different charge states after annealing, which are analyzed by XPS measurements.

• 전기전자학회논문지
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• 제22권4호
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• pp.1226-1229
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• 2018

본 연구에서는 이온주입 된 4H-탄화규소(SiC) 에피 층 위에 환원된 그래핀 산화물 (r-GO)을 보호 층으로 적용하여 고온 열처리 공정 중 발생하는 표면 거칠기 악화를 개선하였다. 실험에 사용 된 4H-SiC 에피 층은 $4^{\circ}$ off-axis n-형 4H-SiC 기판 위에 $10{\mu}m$ 두께로 성장되었다. $n^+$-형 4H-SiC 층을 제공하기 위해 $1.73{\times}10^{15}cm^{-2}$ 농도의 질소를 고온 고에너지 이온주입 공정으로 주입하였고, 보호 층으로 사용한 r-GO는 스프레이 코팅 방식으로 4H-SiC 층 위에 형성하였다. r-GO를 보호 층으로 적용 한 결과, 적용하지 않은 시료에 비해 고온 열처리 후 표면 거칠기 (RMS)가 10배 개선되었으며, 전기적 측정으로 추출한 누설 전류를 통해 표면 거칠기 개선으로 표면 상태가 완화되었음을 확인하였다.

• Journal of Magnetics
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• 제13권1호
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• pp.19-22
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• 2008

ZnO nanotips, grown on c-$Al_2O_3$ and quartz, were implanted variously with 200 keV Fe or Mn ions to a dose level of $5{\times}10^{16}cm^{-2}$. The magnetic properties of these samples were measured using a superconducting quantum interference device (SQUID) magnetometer. Fe-implanted ZnO nanotips grown on c-$Al_2O_3$ showed a coercive field width of 209 Oe and a remanent field of 12% of the saturation magnetization ($2.3{\times}10^{-5}emu$) at 300K for a sample annealed at $700^{\circ}C$ for 20 minutes. The field-cooled and the zero-field-cooled magnetization measurements also showed evidence of ferromagnetism in this sample with an estimated Curie temperature of around 350 K. The Mn-implanted ZnO nanotips grown on c-$Al_2O_3$ showed superparamagnetism resulting from the dominance of a spin-glass phase. The ZnO nanotips grown on quartz and implanted with Fe or Mn showed signs of ferromagnetism, but neither was consistent.

• 전자통신동향분석
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• 제5권1호
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• pp.55-70
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• 1990

SIMOX SOI is known to be one of the most useful technologies for fabrications of new generation ULSI devices. This paper describes the current status of SIMOX SOI technology for ULSI applications. The SIMOX wafer is vertically composed of buried oxide layer and silicon epitaxial layer on top of the silicon substrate. The buried oxide layer is used for the vertical isolation of devices The oxide layer is formed by high energy ion implantation of high dose oxygen into the silicon wafer, followed by high temperature annealing. SIMOX-based CMOS fabrication is transparent to the conventional IC processing steps without well formation. Furthermore, thin film CMOX/SIMOX can overcome the technological limitations which encountered in submicron bulk-based CMOS devices, i.e., soft-error rate, subthreshold slope, threshold voltage roll-off, and hot electron degradation can be improved. SIMOX-based bipolar devices are expected to have high density which comparable to the CMOX circuits. Radiation hardness properties of SIMOX SOI extend its application fields to space and military devices, since military ICs should be operational in radiation-hardened and harsh environments. The cost of SIMOX wafer preparation is high at present, but it is expected to reduce as volume increases. Recent studies about SIMOX SOI technology have demonstrated that the performance of the SIMOX-based submicron devices is superior to the circuits using the bulk silicon.