• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Korean Journal of Optics and Photonics
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• v.3 no.4
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• pp.258-265
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• 1992

A low loss optical waveguide of $P_{2}O_{5}-SiO_{2}$on Si substrate is produced by using the chemical vapour deposition method of $SiO_2$ thin films used in Si technology. Propagation loss of the waveguide layer was 1.65 dB/cm as produced and reduced down to 0.1 dB/cm after heat treatment at $1100^{\circ}C$. By using laser lithography and reactive ion etching method $P_{2}O_{5}-SiO_{2}$ waveguide was produced and subsequently annealed at $1100^{\circ}C$.As a result of this annealing the shape of the waveguide core was changed from rectangular to semi-circular form, and the propagation loss was reduced as down to 0.03 dB/cm at 0.6328$\mu$m and 0.04dB/cm at 1.53$\mu$m. We think that the mechanism of the reduction in propagation loss during the heat treatment is the following: 1) The hydrogen bonding in waveguide layer, which causes absorption loss, is dissociated and diffused out. 2) The roughness of the interface and the micro-structure of the waveguide layer is removed. 3) The irregularities in the cross-sectional shape of the waveguide which was induced during the lithographic process were disappeared by flowing of the waveguide core.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.111-119
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• 2005

Stack specimen with three dimensional interconnection structure through Cu via of $75{\mu}m$ diameter, $90{\mu}m$ height and $150{\mu}m$ pitch was successfully fabricated using subsequent processes of via hole formation with Deep RIE (reactive ion etching), Cu via filling with pulse-reverse electroplating, Si thinning with CMP, photolithography, metal film sputtering, Cu/Sn bump formation, and flip chip bonding. Contact resistance of Cu/Sn bump and Cu via resistance could be determined ken the slope of the daisy chain resistance vs the number of bump joints of the flip chip specimen containing Cu via. When flip- chip bonded at $270^{\circ}C$ for 2 minutes, the contact resistance of the Cu/Sn bump joints of $100{\times}100{\mu}m$ size was 6.7m$\Omega$ and the Cu via resistance of $75{\mu}m$ diameter, $90{\mu}m$ height was 2.3m$\Omega$.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.6
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• pp.34-42
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• 2002

In this paper, we propose a temperature independent the detective voltage source in voltage detector. The value of a detective voltage source is designed to become m times of silicon bandgap voltage at zero absolute temperature. By properly choosing the temperature coefficient of diode, the temperature coefficient of a concave voltage nonlinearities generated by the ${\Delta}V_{BE}$ section of diode between base and emitter of transistors with a different area can be summed with convex nonlinearities the $V_{BE}$ voltage to achieve the near zero temperature coefficient of the detective voltage source. We designed that the value of a detective voltage can be varied by ${\Delta}V_{BE}$, the $V_{BE}$multiplier circuit and resistor. In order to verify the performance of a proposed detective voltage source, we manufactured the voltage detector IC for 1.9V which is fabricated in $6{\mu}m$ Bipolar technology and measured the operating characteristics, the temperature coefficient of a detective voltage. To reduce the deviation of a detective voltage in the IC process step, we introduced a trimming technology, ion implantation and an isotropic etching. In manufactured IC, the detective voltage source could achieve the stable temperature coefficient of 29ppm/$^{\circ}C$ over the temperature range of -30$^{\circ}C$ to 70$^{\circ}C$. The current consumption of a voltage detector constituted by the proposed detective voltage source is $10{\mu}A$ from 1.9V-supply voltage at room temperature.

• Corrosion Science and Technology
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• v.9 no.6
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• pp.276-280
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• 2010

Copper(Cu) as an interconnecting metal layer can replace aluminum (Al) in IC fabrication since Cu has low electrical resistivity, showing high immunity to electromigration compared to Al. However, it is very difficult for copper to be patterned by the dry etching processes. The chemical mechanical polishing (CMP) process has been introduced and widely used as the mainstream patterning technique for Cu in the fabrication of deep submicron integrated circuits in light of its capability to reduce surface roughness. But this process leaves a large amount of residues on the wafer surface, which must be removed by the post-CMP cleaning processes. Copper corrosion is one of the critical issues for the copper metallization process. Thus, in order to understand the copper corrosion problems in post-CMP cleaning solutions and study the effects of DC biases and post-CMP cleaning solution concentrations on the Cu film, a constant voltage was supplied at various concentrations, and then the output currents were measured and recorded with time. Most of the cases, the current was steadily decreased (i.e. resistance was increased by the oxidation). In the lowest concentration case only, the current was steadily increased with the scarce fluctuations. The higher the constant supplied DC voltage values, the higher the initial output current and the saturated current values. However the time to be taken for it to be saturated was almost the same for all the DC supplied voltage values. It was indicated that the oxide formation was not dependent on the supplied voltage values and 1 V was more than enough to form the oxide. With applied voltages lower than 3 V combined with any concentration, the perforation through the oxide film rarely took place due to the insufficient driving force (voltage) and the copper oxidation ceased. However, with the voltage higher than 3 V, the copper ions were started to diffuse out through the oxide film and thus made pores to be formed on the oxide surface, causing the current to increase and a part of the exposed copper film inside the pores gets back to be oxidized and the rest of it was remained without any further oxidation, causing the current back to decrease a little bit. With increasing the applied DC bias value, the shorter time to be taken for copper ions to be diffused out through the copper oxide film. From the discussions above, it could be concluded that the oxide film was formed and grown by the copper ion diffusion first and then the reaction with any oxidant in the post-CMP cleaning solution.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.214-214
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• 1999

다이아몬드를 반도체용 열방산용기판 등으로 사용하기 위해서는 수백 $\mu\textrm{m}$ 두께의 대면적 웨이퍼가 요구된다. 이를 위해서 DC are jet CVD, MW PACVD, DC PACVD 등이 개발되어, 현재 4"에서 8"까지의 많은 문제를 일으키고 있다. 본 연구에서는 multi-cathode DC PACVD법에 의한 4" 다이아몬드 웨이퍼의 합성과 합성된 막의 특성변화에 대한 연구를 수행하였다. 또한, 웨이퍼의 휨과 crack 발생거동과 대한 고찰을 통래 휨과 crack이 없는 웨이퍼의 제작방법을 고안하였다. 사용된 음극의 수는 일곱 개이며, 투입된 power는 각 음극 당 약 2.5kW(4.1 A-600V)이었다. 사용된 기판의 크기는 직경 4"이었다. 합성압력은 100Torr, 가스유량은 150sccm, 증착온도는 125$0^{\circ}C$~131$0^{\circ}C$, 수소가스네 메탄조성은 5%~8%이었다. 합성 중 막에 인가되는 응력은 합성 중 증착온도의 변화에 의해 제어하였다. 막의 결정도는 Raman spectroscopy 및 열전도도를 측정을 통해 분석하였다. 성장속도 및 다이아몬드 peak의 반가폭은 메탄조성 증가(5%~8%)에 따라 증가하여 각각 6.6~10.5$\mu\textrm{m}$/h 및 3.8~5.2 cm-1의 분포를 보였다. 6%CH4 및 7%CH4에서 합성된 웨이퍼에서 측정된 막의 열전도도는 11W/cmK~13W/cmK 정도로 높게 나타났다. 막두께의 uniformity는 최대 3.5%로 매우 균일하였다. 막에 인가되는 응력의 제어로 직경 4"k 합성면적에서 두께 1mm 이상의 균열 및 휨이 없는 다이아몬드 자유막 웨이퍼를 합성할 수 있었다.다이아몬드 자유막 웨이퍼를 합성할 수 있었다.active ion에 의해 sputtering 이 된다. 이때 plasma 처리기의 polymer 기판 후면에 magnet를 설치하여 높은 ionization을 발생시켜 처리 효과를 한층 높여 주었다. 이 plasma 처리는 표면 청정화, 표면 etching 이 동시에 행하는 것과 함께 장시간 처리에 의해 표면에서는 미세한 과, C=C기, -C-O-의 극성기의 도입에 의한 표면 개량이 된다는 것을 관찰할 수 있다. OPP polymer 표면을 Ar 100%로 plasma 처리한 경우 C-O, C=O 등의 carbonyl가 발생됨을 알 수 있었다. C-O, C=O 등의 carbynyl polor group이 도입됨에 따라 sputter된 Al의 접착력이 향상됨을 알 수 있으며, TEM 관찰 결과 grain size도 상당히 작아짐을 알 수 있었다.onte-Carlo 방법으로 처리하였다. 정지기장해석의 경우 상용 S/W인 Vector Fields를 사용하였다. 이를 통해 sputter 내 플라즈마 특성, target으로 입사하는 이온에너지 및 각 분포, 이들이 target erosion 형상에 미치는 영향을 살펴보았다. 또한 이들 결과로부터 간단한 sputtering 모델을 사용하여 target으로부터 sputter된 입자들이 substrate에 부착되는 현상을 Monte-Carlo 방법으로 추적하여 성막특성도 살펴보았다.다.다양한 기능을 가진 신소재 제조에 있다. 또한 경제적인 측면에서도 고부가 가치의 제품 개발에 따른 새로운 수요 창출과 수익률 향상, 기존의 기능성 안료를 나노(nano)화하여 나노 입자를 제조, 기존의 기능성 안료에 대한 비용 절감 효과등을 유도 할 수 있다. 역시 기술적인 측면에서도 특수소재 개발에 있어 최적의 나노 입자 제어기술 개발 및 나노입자를 기능성 소재로 사용하여 새로운 제품의 제조와 고압 기상

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.257-257
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• 2007

고밀도 FeRAM (Ferroe!ectric Random Access Memory) 소자를 개발하기 위해서는 강유전체 물질을 이용한 안정적인 스텍형의 커패시터 개발이 필수적이다. 특히 $(Bi,La)_4Ti_3O_{12}$ (BLT) 강유전체 물질을 이용하는 경우에는 낮은 열처리 온도에서도 균질하고 높은 값의 잔류 분극 값을 확보하는 것이 가장 중요한 과제 중의 하나이다. 불행히도, BLT 물질은 a-축으로는 약 $50\;{\mu}C/cm^2$ 정도의 높은 잔류 분극 값을 갖지만, c-축 방향으로는 $4\;{\mu}C/cm^2$ 정도의 낮은 잔류 분극 값을 나타내는 동의 강한 비등방성 특성을 보인다. 따라서 BLT 박막에서 각각 입자들의 크기 및 결정 방향성을 세밀하게 제어하는 것은 무엇보다 중요하다. 본 연구에서는 16 Mb의 1T/1C (1-transistor/1-capacitor) 형의 FeRAM 소자를 BLT 박막을 적용하여 제작하였다. 솔-젤 (sol-gel) 용액을 이용하여 스핀코팅법으로 BLT 박막을 증착하고, 후속 열처리 공정을 RTP (rapid thermal process) 공정을 이용하여 수행하였다. 커패시터의 하부 전극 및 상부 전극은 각각 Pt/IrOx/lr 및 Pt을 적용하였다. 반응성 이온 에칭 (RIE: reactive ion etching) 공정을 이용하여 커패시터를 형성시킨 후, 32k-array (unit capacitor: $0.68\;{\mu}m$) 패턴에서 측정한 스위칭 분극 (dP=P*-P^) 값은 약 $16\;{\mu}C/cm^2$ 정도이고, 웨이퍼 내에서의 균일도도 2.8% 정도로 매우 우수한 특성을 보였다. 그러나 단위 셀들의 특성을 평가하기 위하여 bit-line의 전압을 측정한 결과, 약 10% 정도의 커패시터에서 불량이 발생하였다. 그리고 이러한 불량 젤들은 매우 불규칙적으로 분포함을 확인할 수 있었다. 이러한 불량 원인을 파악하기 위하여 양호한 젤과 불량이 발생한 셀에서의 BLT 박막의 미세구조를 분석하였다. 양호한 셀의 BLT 박막 입자들은 불량한 셀에 비하여 작고 비교적 균일한 크기를 갖고 있었다. 이에 비하여 불량한 셀에서의 BLT 박막에는 과대 성장한 입자들이 존재하고 이에 따라서 입자 크기가 매우 불균질한 것으로 확인되었다. 또 이러한 과대 성장한 입자들은 거의 모두 c-축 배향성을 나타내었다. 이상의 실험 결과들로부터, BLT 박막을 이용하여 제작한 FeRAM 소자에서 발생하는 불규칙한 셀 불량의 주된 원인은 c-축 배향성을 갖는 과대 성장한 입자의 생성임을 알 수 있었다. 즉 BLT 박막을 이용하여 FeRAM 소자를 제작하는 경우, 균일한 크기의 입자 및 c-축 배향성의 입자 억제가 매우 중요한 기술적 요소임을 알 수 있었다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.4
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• pp.1-7
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• 2017

Cobalt silicide was used as a counter electrode in order to confirm its reliability in dye-sensitized solar cell (DSSC) devices. 100 nm-Co/300 nm-Si/quartz was formed by an evaporator and cobalt silicide was formed by vacuum heat treatment at $700^{\circ}C$ for 60 min to form approximately 350 nm-CoSi. This process was followed by etching in $80^{\circ}C$-30% $H_2SO_4$ to remove the cobalt residue on the cobalt silicide surface. Also, for the comparison against Pt, we prepared a 100 nm-Pt/glass counter electrode. Cobalt silicide was used for the counter electrode in order to confirm its reliability in DSSC devices and maintained for 0, 168, 336, 504, 672, and 840 hours at $80^{\circ}C$. The photovoltaic properties of the DSSCs employing cobalt silicide were confirmed by using a simulator and potentiostat. Cyclic-voltammetry, field emission scanning electron microscopy, focused ion beam scanning electron microscopy, and energy dispersive spectrometry analyses were used to confirm the catalytic activity, microstructure, and composition, respectively. The energy conversion efficiency (ECE) as a function of time and ECE of the DSSC with Pt and CoSi counter electrodes were maintained for 504 hours. However, after 672 hours, the ECEs decreased to a half of their initial values. The results of the catalytic activity analysis showed that the catalytic activities of the Pt and CoSi counter electrodes decreased to 64% and 57% of their initial values, respectively(after 840 hours). The microstructure analysis showed that the CoSi layer improved the durability in the electrolyte, but because the stress concentrates on the contact surface between the lower quartz substrate and the CoSi layer, cracks are formed locally and flaking occurs. Thus, deterioration occurs due to the residual stress built up during the silicidation of the CoSi counter electrode, so it is necessary to take measures against these residual stresses, in order to ensure the reliability of the electrode.