• ETRI Journal
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• 제27권5호
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• pp.511-524
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• 2005

In this paper, we propose a novel hardware architecture for an intra-prediction, integer transform, quantization, inverse integer transform, inverse quantization, and mode decision module for the macroblock engine of a new video coding standard, H.264. To reduce the cycle of intra prediction, transform/quantization, and inverse quantization/inverse transform of H.264, a reduction method for cycle overhead in the case of I16MB mode is proposed. This method can process one macroblock for 927 cycles for all cases of macroblock type by processing $4{\times}4$ Hadamard transform and quantization during $16{\times}16$ prediction. This module was designed using Verilog Hardware Description Language (HDL) and operates with a 54 MHz clock using the Hynix $0.35 {\mu}m$ TLM (triple layer metal) library.

• 전자공학회논문지
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• 제53권4호
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• pp.106-114
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• 2016

본 논문에서는 VP9 디코더에 대한 행렬 기반의 정수형 역변환 구조를 제안한다. 제안하는 구조는 DCT(Discreste Cosine Transform), ADST(Asymmetric Discrete Sine Transform) 그리고 WHT(Walsh-Hadamard Transform)에 대한 알고리즘을 공유하며 버터플라이구조보다 하드웨어 리소스를 줄이고 제어하기 쉬운 하드웨어 구조이다. VP9 구글 모델 내 정수형 역변환은 버터플라이구조 기반의 정수형 역변환 구조를 가진다. 일반적인 버터플라이구조와는 달리 구글모델 내 정수형 역변환은 각 단계마다 라운드 쉬프트 연산기를 가지며, 비대칭 구조의 사인 변환을 포함한다. 따라서 제안하는 구조는 모든 역변환 모드에 대해 행렬계수 값을 근사하고, 이 계수 값을 이용하여 행렬연산 방식을 사용한다. 본 논문의 기술을 사용하면 역변환 알고리즘에 대한 모드별 동작 공유 및 버터플라이구조에 비해 곱셈기 수를 2배가량 감소시킬 수 있다. 그래서 하드웨어 리소스를 효율적으로 관리가 가능해진다.

• 한국통신학회논문지
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• 제28권12C호
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• pp.1182-1191
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• 2003

본 논문에서는 H.264의 정수 변환 모듈, 양자화 모듈, 역양자화 모듈, 정수 역변환 모듈에 대한 하드웨어 구조를 제안한다. 새로운 동영상 압축기술인 H.264의 전체 구성 중에서 핵심 부분인 동영상 데이터의 영역 변환 및 양자화 기능들을 하드웨어로 설계할 수 있도록 알고리즘을 기술하고, 저전력 설계를 위하여 하드웨어 사이즈를 최소화하도록 구조를 정하였다. 구현된 전체 모듈들은 PCI 인터페이스를 통한 Altera APEX-II FPGA 구성과 삼성 STD130 0.18um CMOS Cell Library를 이용하여 각각 합성하고 검증하였다. 이렇게 검증된 구조의 성능은 ASIC으로 구현하였을 경우 최대 동작 주파수가 100MHz이며, QCIF의 사이즈 기준으로 초당 최대 1295 프레임의 계산을 수행할 수 있으며, 이는 하드웨어 기반의 H.264 실시간 부호화기를 설계하기에 적합한 구조임을 보여준다.

• Journal of electromagnetic engineering and science
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• 제6권4호
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• pp.244-252
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• 2006

A block Jacket transform and. its block inverse Jacket transformn have recently been reported in the paper 'Fast block inverse Jacket transform'. But the multiplication of the block Jacket transform and the corresponding block inverse Jacket transform is not equal to the identity transform, which does not conform to the mathematical rule. In this paper, new binary block Jacket transforms and the corresponding binary block inverse Jacket transforms of orders $N=2^k,\;3^k\;and\;5^k$ for integer values k are proposed and the mathematical proofs are also presented. With the aid of the Kronecker product of the lower order Jacket matrix and the identity matrix, the fast algorithms for realizing these transforms are obtained. Due to the simple inverse, fast algorithm and prime based $P^k$ order of proposed binary block inverse Jacket transform, it can be applied in communications such as space time block code design, signal processing, LDPC coding and information theory. Application of circular permutation matrix(CPM) binary low density quasi block Jacket matrix is also introduced in this paper which is useful in coding theory.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권4호
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• pp.237-242
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• 2005

H.264/AVC adopts new features compared with previous multimedia algorithms. It is inefficient to implement some of the new blocks using existing DSP instructions. Hence, new instructions are required to implement H.264/AVC. This paper proposes novel instructions for intra-prediction, in-loop deblocking filter, entropy coding and integer transform. Performance comparisons show that the required computation cycles for the in-loop deblocking filter can be reduced about $20{\sim}25%$. This paper also proposes new instructions for the integer transform. The proposed instructions can execute one dimension forward/inverse integer transform. The integer transform can be implemented using much smaller hardware size than existing DSPs.

• 전자공학회논문지B
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• 제32B권9호
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• pp.1207-1214
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• 1995

We present an optimized integer cosine transform(OICT) as an alternative approach to the conventional discrete cosine transform(DCT), and its fast computational algorithm. In the actual implementation of the OICT, we have used the techniques similar to those of the orthogonal integer transform(OIT). The normalization factors are approximated to single one while keeping the reconstruction error at the best tolerable level. By obtaining a single normalization factor, both forward and inverse transform are performed using only the integers. However, there are so many sets of integers that are selected in the above manner, the best OICT matrix obtained through value minimizing the Hibert-Schmidt norm and achieving fast computational algorithm. Using matrix decomposing, a fast algorithm for efficient computation of the order-8 OICT is developed, which is minimized to 20 integer multiplications. This enables us to implement a high performance 2-D DCT processor by replacing the floating point operations by the integer number operations. We have also run the simulation to test the performance of the order-8 OICT with the transform efficiency, maximum reducible bits, and mean square error for the Wiener filter. When the results are compared to those of the DCT and OIT, the OICT has out-performed them all. Furthermore, when the conventional DCT coefficients are reduced to 7-bit as those of the OICT, the resulting reconstructed images were critically impaired losing the orthogonal property of the original DCT. However, the 7-bit OICT maintains a zero mean square reconstruction error.

• 대한전자공학회논문지SD
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• 제49권8호
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• pp.27-34
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• 2012

본 논문에서 H.264표준을 위해 2차원 $8{\times}8$ 순방향/역방향 정수 DCT 변환을 빠르고 효율적으로 계산할 수 있는 알고리즘을 제안한다. 순방향/역방향 변환은 간단한 시프트와 덧셈 동작을 사용하여 계산 복잡도를 줄였으며, DCT 연산에 메모리를 사용하지 않으므로 해서 불필요한 자원소모를 줄였다. 제안된 파이프라인 아키텍처의 최대 동작 주파수는 1.184GHz이며, 합성결과는 44864 게이트가 사용되어 25.27Gpixels/sec의 스루풋을 보여준다. 면적 비율에 비해 높은 스루풋으로 인해, 제안된 설계는 H.264/AVC 고해상도 비디오기술의 실시간 처리에 효율적으로 사용할 수 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.247-253
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• 2007

In this paper, a high throughput multiple transform architecture for H.264 Fidelity Range Extensions (FRExt) is proposed. New techniques are adopted which (1) regularize the $8{\times}8$ integer forward and inverse DCT transform matrices, (2) divide them into four $4{\times}4$ sub-matrices so that simple fast butterfly algorithm can be used, (3) because of the similarity of the sub-matrices, mixed butterflies are proposed that all the sub-matrices of $8{\times}8$ and matrices of $4{\times}4$ forward DCT (FDCT), inverse DCT (IDCT) and Hadamard transform can be merged together. Based on these techniques, a hardware architecture is realized which can achieve throughput of 1.488Gpixel/s when processing either $4{\times}4\;or\;8{\times}8$ transform. With such high throughput, the design can satisfy the critical requirement of the real-time multi-transform processing of High Definition (HD) applications such as High Definition DVD (HD-DVD) ($1920{\times}1080@60Hz$) in H.264/AVC FRExt. This work has been synthesized using Rohm 0.18um library. The design can work on a frequency of 93MHz and throughput of 1.488Gpixel/s with a cost of 56440 gates.

• 전자공학회논문지T
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• 제36T권1호
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• pp.1-7
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• 1999

본 논문에서는 실시간 영상처리 시스템나 HDTV에서의 영상신호 압축 및 복원의 실시간처리를 위해 사용하는 고성능 2-D DCT 프로세서의 VLSI 구조를 최적화 정수형 여현 변환(OICT)의 고속 연산 알고리즘을 이용하여 구현하였다. OICT의 고속 연산 알고리즘의 계수는 정수값이어서 변환시 정수형 연산을 수행하게 되므로 부동소수점 연산을 수행하는 DCT에 비해 전체적으로 하드웨어의 복잡도와 속도를 향상시킬 수 있다. 제안한 VLSI 구조는 이러한 OICT의 장점을 설려 곱셈기를 입력값의 쉬프트와 덧셈기만으로 구성하여 고속연산을 수행하게 하므로써 비용과 속도를 개선할 수 있었다.

• 대한기계학회논문집A
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• 제28권10호
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• pp.1574-1582
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• 2004

Binary manipulators have recently received much attention due to hyper-redundancy, light weight, good controllability and high reliability. The precise positioning of the manipulator end-effecter requires the use of many modules, which results in a high-dimensional workspace. When the workspace dimension is large, existing inverse kinematics methods such as the Ebert-Uphoff algorithm may require impractically large memory size in determining the binary positions of all actuators. To overcome this limitation, we propose a new inverse kinematics algorithm: the inverse kinematics problem is formulated as an optimization problem using real-valued design variables, The key procedure in this approach is to transform the integer-variable optimization problem to a real-variable optimization problem and to push the real-valued design variables as closely as possible to the permissible binary values. Since the actual optimization is performed in real-valued design variables, the design sensitivity becomes readily available, and the optimization method becomes extremely efficient. Because the proposed formulation is quite general, other design considerations such as operation power minimization can be easily considered.