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High Throughput Parallel Design of 2-D $8{\times}8$ Integer Transforms for H.264/AVC  

Sharma, Meeturani (Department of Electronic Engineering, Konkuk University)
Tiwari, Honey (Department of Electronic Engineering, Konkuk University)
Cho, Yong-Beom (Department of Electronic Engineering, Konkuk University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.49, no.8, 2012 , pp. 27-34 More about this Journal
Abstract
In this paper, the implementation of high throughput two-dimensional (2-D) $8{\times}8$ forward and inverse integer DCT transform for H.264 is presented. The forward and inverse transforms are represented using simple shift and addition operations. Matrix decomposition and matrix operation such as the Kronecker product and direct sum are used to reduce the computation complexity. The proposed design uses integer computations and does not use transpose memory and hence, the resource consumption is also reduced. The maximum operating frequency of the proposed pipelined architecture is 1.184 GHz, which achieves 25.27 Gpixels/sec throughput rate with the hardware cost of 44864 gates. High throughput and low hardware makes the proposed design useful for real time H.264/AVC high definition processing.
Keywords
DCT; dual clock architecture; H.264/AVC; IDCT; integer transform;
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