JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

A High Throughput Multiple Transform Architecture for H.264/AVC Fidelity Range Extensions

  • Ma, Yao (Graduate School of Information, Production and Systems, Waseda University) ;
  • Song, Yang (Graduate School of Information, Production and Systems, Waseda University) ;
  • Ikenaga, Takeshi (Graduate School of Information, Production and Systems, Waseda University) ;
  • Goto, Satoshi (Graduate School of Information, Production and Systems, Waseda University)
  • Published : 2007.12.31
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, a high throughput multiple transform architecture for H.264 Fidelity Range Extensions (FRExt) is proposed. New techniques are adopted which (1) regularize the $8{\times}8$ integer forward and inverse DCT transform matrices, (2) divide them into four $4{\times}4$ sub-matrices so that simple fast butterfly algorithm can be used, (3) because of the similarity of the sub-matrices, mixed butterflies are proposed that all the sub-matrices of $8{\times}8$ and matrices of $4{\times}4$ forward DCT (FDCT), inverse DCT (IDCT) and Hadamard transform can be merged together. Based on these techniques, a hardware architecture is realized which can achieve throughput of 1.488Gpixel/s when processing either $4{\times}4\;or\;8{\times}8$ transform. With such high throughput, the design can satisfy the critical requirement of the real-time multi-transform processing of High Definition (HD) applications such as High Definition DVD (HD-DVD) ($1920{\times}1080@60Hz$) in H.264/AVC FRExt. This work has been synthesized using Rohm 0.18um library. The design can work on a frequency of 93MHz and throughput of 1.488Gpixel/s with a cost of 56440 gates.

Keywords

References

  1. C. Lauterback, W. Weber, and D. Romer, 'Charge-sharing concept and new clocking scheme for power efficiency and electromagnetic emission improvement of boosted charge pumps,' IEEE J Solid State Circuits, vol.35, pp.7l9-723, May. 2000
  2. T. Tanzawa and S. Atsumi, 'Optimization of wordline booster circuits for low-voltage flash memories,' IEEE J Solid State Circuits, vol.34, pp.1091-1098, Aug. 1999 https://doi.org/10.1109/4.777107
  3. T. Wiegand, G. J. Sullivan, G. Bjtegaard, and A. Luthra, 'Overview of the H.264/AVC Video Coding Standard,' IEEE Trans. on CSVT, vol. 13, pp. 560-576, Jun. 2003
  4. D. Marpe, T. Wiegand, and S. Gordon, 'H.264/MPEG4-AVC Fidelity Range Extensions: Tools, Profiles, Performance, and Application Areas,' IEEE Int. Conf on Image Processing (ICIP), pp.593- 596,Sep.2005
  5. T-C. Wang, Y-W. Huang, H-C. Fang, and L-G. Chen, 'Parallel 4x4 2D Transform and Inverse Transform Architecture for MPEG-4 AVC/H.264,' IEEE Int. Symp. on Circuits and Systems, pp. 800-803, May. 2003
  6. K. Chen and J. Guo, 'A High-Performance Direct 2D Transform Coding IP Design for MPEG-4 AVC/H.264,' IEEE Trans on CSVT, vol. 16, pp. 472-483, Apr. 2006
  7. I. Amer, W. Badawy, and G. Jullien, 'A HighPerformance Hardware Implementation of the Hol64 Simplified 8x8 Transformation and Quantization,' IEEE Int. Conf on Acoustics, Speech, and Signal Processing, Vol. 2, pp. 1137-1140,Mar. 2005
  8. J. Bruguera and R. Osorio, 'A Unified Architecture for H.264 Multiple Block-size DCT with Fast and Low Cost Quantization,' EUROMICRO Conference on Digital System Design (DSD), pp. 407-414, 2006