• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.13-20
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• 2008

This paper describes the methods of spacer-fabrication for wafer-level CIS(CMOS Image Sensor) assembly. We propose three methods using SU-8, PDMS and Si-interposer for the spacer-fabrication. For SU-8 spacer, novel wafer rotating system is developed and for PDMS(poly-dimethyl siloxane) spacer, new fabrication-method is used to bond with alignment of glass/PDMS/glass structure. And for Si-interposer, DFR(Dry Film Resist) is used as adhesive layer. The spacer using Si-interposer has the strongest bonding strength and the strength is 32.3MPa with shear.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.3-17
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• 2003

.Package Trend -> Memory : Lighter, Thinner, Smaller & High Density => SiP, 3D Stack -> MPU : High Pin Counts & Multi-functional => FCBGA .Interposer Trend -> Via - Unfilled Via => Filled Via - Staggered Via => Stacked Via -> Emergence of All-layer Build-up Processes -> Interposer Material Requirement => Low CTE, Low $D_{k}$, Low $D_{f}$, Halogen-free .New Technology Concept -> Embedded Passives, Imprint, MLTS, BBUL etc.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.3
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• pp.25-29
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• 2022

Recently, the importance of electronic packaging technology has been attracting attention, and heterogeneous integration technology in which chips are stacked out-of-plane direction is being applied to the electronic packaging field. The 2.5D integration circuit is a technology for stacking chips using an interposer including TSV, and is widely used already. Therefore, it is necessary to make the interposer mechanically reliable in the packaging process that undergoes various thermal processes and mechanical loadings. Considering the structural characteristics of the interposer on which several thin films are deposited, thermal stress due to the difference in thermal expansion coefficients of materials can have a great effect on reliability. In this study, the mechanical reliability of the metal pad for wire bonding on the silicon interposer against thermal stress was evaluated. After heating the interposer to the solder reflow temperature, the delamination of the metal pad that occurred during cooling was observed and the mechanism was investigated. In addition, it was confirmed that the high cooling rate and the defect caused by handling promote delamination of the metal pads.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.4
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• pp.97-101
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• 2021

In this study, Insertion loss according to the structural variant of interposer to Through Silicon Via (TSV) and Redistributed Layer (RDL) was studied through design of experiment. 3-Factors was considered as a variant, TSV depth, TSV diameter, RDL width with factor arrangement method and the response surface method from 400 MHz to 20 GHz. As a result, it was confirmed that as the frequency increased, the effect of RDL width was decreased and the effect of TSV depth and TSV diameter was increased. Also within the analysis range, to increasing RDL width, decreasing TSV depth, and fixing TSV diameter about 10.7 ㎛ was observed optimal result of Insertion loss.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.43-51
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• 2014

In 3-dimensional (3D) integrated package, thermal management is one of the critical issues due to the high heat flux generated by stacked multi-functional chips in miniature packages. In this study, we used numerical simulation method to analyze the thermal behaviors, and investigated the thermal issues of 3D package using TSV (through-silicon-via) technology for mobile application. The 3D integrated package consists of up to 8 TSV memory chips and one logic chip with a interposer which has regularly embedded TSVs. Thermal performances and characteristics of glass and silicon interposers were compared. Thermal characteristics of logic and memory chips are also investigated. The effects of numbers of the stacked chip, size of the interposer and TSV via on the thermal behavior of 3D package were investigated. Numerical analysis of the junction temperature, thermal resistance, and heat flux for 3D TSV package was performed under normal operating and high performance operation conditions, respectively. Based on the simulation results, we proposed an effective integration scheme of the memory and logic chips to minimize the temperature rise of the package. The results will be useful of design optimization and provide a thermal design guideline for reliable and high performance 3D TSV package.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.40-50
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• 2023

Recently, the number of components of smartphones increases rapidly, while the PCB size continuously decreases. Therefore, 3D technology with a stacked PCB has been developed to improve component density in smartphone. For the s tacked PCB, it i s very important to obtain solder bonding quality between PCBs. We investigated the effects of the properties, thickness, and number of layers of interposer PCB and sub PCB on warpage of PCB through experimental and numerical analysis to improve the reliability of the stacked PCB. The warpage of the interposer PCB decreased as the thermal expansion coefficient (CTE) of the prepreg decreased, and decreased as the glass transition temperature (Tg) increased. However, if temperature is 240℃ or higher, the reduction of warpage is not large. As FR-5 was applied, the warpage decreased more compared to FR-4, and the higher the number and thickness of the prepreg, the lower the warpage. For sub PCB, the CTE was more important for warpage than Tg of the prepreg, and increase in prepreg thickness was more effective in reducing the warpage. The shear tests indicated that the dummy pad design increased bonding strength. The tumble tests indicated that crack occurrence rate was greatly reduced with the dummy pad.

• International journal of advanced smart convergence
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• v.11 no.2
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• pp.53-58
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• 2022

In this paper, w-band frequency synthesizer was developed for frequency-modulated continuous wave (FMCW) radar sensors. To achieve a small size and high performance, We designed and manufactured w-band MMIC chips such as up-converter one-chip, multiplier, DA (Drive Amplifier) MMIC(Monolithic Microwave Integrated Circuit), etc. And interposer technology was applied between the W-band multiplier and the DA MMIC chip. As a result, the measured phase noise was -106.10 dBc@1MHz offset, and the frequency switching time of the frequency synthesizer was less than 0.1 usec. Compared with the w-band frequency synthesizer using purchased chips, the developed frequency synthesizer showed better performance.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.40 no.11
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• pp.755-759
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• 2016

The use of heat pipes in the electronic telecommunication field is increasing. Among the various types of heat pipes, the thin flat heat pipe has relatively high applicability compared with the circular heat pipe in the electronic packaging application. The thin flat heat pipe based on extrusion fabrication has a simple capillary wick structure consisting of rectangular cross sectional grooves on the inner wall of the pipe. Although the groove serves as a simple capillary wick, and many such grooves are provided on the inner wall, it is difficult for the grooves to realize a sufficiently high capillary force. In the present study, a thin flat heat pipe with a wire bundle was developed to overcome the drawback of poor capillary force in the thin flat heat pipe with grooves, and was evaluated by conducting tests. In the performance test, the thin flat heat pipe with the wire bundle showed a lower thermal resistance of approximately 3.4 times, and a higher heat transfer rate of approximately 3.8 times with respect to the thin flat heat pipe with grooves as the capillary wick respectively. The possibility of using the wire bundle as a capillary wick in the heat pipe was validated in the present study; further study for commercializing this concept will be taken up in the future.