• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.6
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• pp.580-585
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• 2004

Silicon dioxide (SiO$_2$) is widely used as a gate dielectric material for thin film transistors (TFT) and semiconductor devices. In this paper, SiO$_2$ films were grown by APCVD(Atmospheric Pressure chemical vapor deposition) at the high temperature. Experimental investigations were carried out as a function of $O_2$ gas flow ratios from 0 to 200 1pm. This article presents the SiO$_2$ gate dielectric studies in terms of deposition rate, refrative index, FT-IR, C-V for the gate dielectric layer of thin film transistor applications. We also study defect passivation technique for improvement interface or surface properties in thin films. Our passivation technique is Forming Gas Annealing treatment. FGA acts passivation of interface and surface impurity or defects in SiO$_2$ film. We used RTP system for FGA and gained results that reduced surface fixed charge and trap density of midgap value.

• Journal of Information Display
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• v.1 no.1
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• pp.25-28
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• 2000

We propose a new in-situ fluorine passivation of poly-Si TFTs using excimer laser annealing to reduce the trap state density and improve reliability significantly. To investigate the effect of an in-situ fluorine passivation, we have fabricated fluorine-passivated p-channel poly-Si TFTs and examined their electrical characteristics and stability. A new in-situ fluorine passivation brought about an improvement in electrical characteristic. Such improvement is due to the formation of stronger Si-F bonds than Si-H bonds in poly-Si channel and $SiO_2$/Poly-Si interface.

• ETRI Journal
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• v.17 no.4
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• pp.1-12
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• 1996

A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current ($I_{DS}-V_{DS}$) curves, substrate resistance effect on the $I_{DS}-V_{DS}$ curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1428-1430
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• 1996

Thin Silicon oxynitride(SiON) films have been chemically deposited using 193nm ArF Excimer Laser CVD, with $Si_{2}H_{8}$, $N_{2}O$, and $NH_3$ as the reactive gases and $N_2$ as the carrier gas. Experimental results show that deposition rate and refractive index have a strong dependence on substrate temperature, chamber pressure, gas ratio, laser power and laser beam height. Electrical characterization of oxynitride films demonstrates that for $NH_{3}/N_{2}O$ flow ratios ranging from 0.25 to 1, the leakage currents, the interface trap density and the capacitances (dielect ric constant) increase and the dielectric breakdown fields decrease

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.171-174
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• 1994

The drive towards ultra-large-scale integrated circuits a continuous intermetal dielectric films for multi layer interconection. Optimum condition of remote plasma enhanced chemical vapour deposition(RPECVD) was achieved by orthogonal array method. Chracteristics of SiO$_2$ films deposited by using remote PECVD with N$_2$O gas were investigated. Etching rate of SiO$_2$ films in P-echant was about 6[A/s] that was the same as the thermal oxide. The films a showed high breakdown voltage of 7(MV/cm) and a resistivity of Bx10$\^$13/[$\Omega$cm] at 7(MV/cm). The interface Trap density of SiO$_2$ has been shown excel lent properties of 5x10$\^$10/[/$\textrm{cm}^2$eV]. It was observed that the dielectric constant dropped to a value of 4. 29 for 150 [W] RF power.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.550-552
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• 2009

The negative bias temperature instability on LTPS TFTs in a darkened and an illuminated environment was investigated. Experimental results reveal that the generation of interface state density showed no change between the different NBTI stresses. The degradation of the grain boundary trap under illumination was more significant than for the darkened environment.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.41 no.7
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• pp.760-765
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• 1992

The material properties and the TFT characteristics fabricated on SiOS12T substrate by LPCVD using SiHS14T gas were investigated. The deposition rate showed Arrhenius behavior with an activation energy of 31Kcal/mol. And the transition temperature form amorphous to crystalline deposition was observed at 570$^{\circ}C$-580$^{\circ}C$. The strong(220) texture was observed as the deposition temperature increases. XRD analysis showed that the film texture of the as-deposited polycrystalline silicon does not change after annealing at 850$^{\circ}C$. The fabricated TFT's based on the as-deposited amorphous film showed superior electrical characteristics to those of the as-deposited polycrystalline films. It is considered that the different electrical characteristics result from the difference of flat band voltage(VS1FBT) due to the interface trap density between the gate oxide and the active channel.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.473-476
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• 1987

Low temperature phosphorus-nitride CVD was newly developed for a high quality gate insulator on InP substrate. This film showed the Poole-Frenkel type conduction in high electric field with resistivity higher than $1{\times}10^{14}$ ohm-cm near the electric field of $1{\times}10^7\;volt/cm$. The C-V hysteresis width was very small as 0.17 volt. The density of interface trap states was $2{\times}10^{11}cm^{-2}ev^{-1}$ below the conduction band edge of InP substrate. Effective electron mobility was about $1200-1500\;cm^2/Vsec$ and showed the instability of PN-InP MISFETs drain current reduced less than 10 percent for the period $0.5-10^3sec$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.11-12
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• 2007

The electrical characteristics of strained-SOI wafer were evaluated by using pseudo-MOSFET. The electrical characteristics of sSOI pseudo-MOSFET were superior to conventional SOI device. Moreover, the electrical characteristics were enhanced by forming gas anneal due to reduction of back interface trap density between substrate and buried oxide.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.26-26
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• 2000

High quality epitaxial Y2O3 thin films were prepared on Si(111) and (001) substaretes by using ion beam assisted deposition. As a substrate, clean and chemically oxidized Si wafers were used and the effects of surface state on the film crystallinity were investigated. The crystalline quality of the films were estimated by x-ray scattering, rutherford backscattering spectroscopy/channeling, and high-resolution transmission electron microscopy (HRTEM). The interaction between Y and Si atoms interfere the nucleation of Y2O3 at the initial growth stage, it could be suppressed by the interface SiO2 layer. Therefore, SiO2 layer of the 4-6 layers, which have been known for hindering the crystal growth, could rather enhance the nucleation of the Y2O3 , and the high quality epitaxial film could be grown successfully. Electrical properties of Y2O3 films on Si(001) were measured by C-V and I-V, which revealed that the oxide trap charge density of the film was 1.8$\times$10-8C/$\textrm{cm}^2$ and the breakdown field strength was about 10MV/cm.