• 한국재료학회:학술대회논문집
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• 한국재료학회 2012년도 춘계학술발표대회
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• pp.59.1-59.1
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• 2012

Organic thin-film transistors (OTFTs) with printable semiconductors are promising candidate devices for flexible active-matrix (AM) display applications. Yet, stable operation of actual display panels driven by OTFTs has seldom been reported up to date. Here, we demonstrate a flexible reflective type polymer dispersed liquid crystal (PDLC) display, in which inkjet-printed OTFT arrays are used as driving elements with excellent areal uniformity in terms of device performance. As the active semiconductor, a novel, ambient processable conjugated copolymer was synthesized. The stability of the devices with respect to electrical bias stress was improved by applying a channel-passivation layer, which suppresses the environmental effects and hence reduces the density of trap states at the channel/dielectric interface. The combination of high performance and high stability OTFT devices enabled the successful realization of stable operating flexible color-displays by inkjet-printing.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권9호
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• pp.502-509
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• 2000

In this paper in order to evaluat quantitavely the formation mechanism of space charge and its effects on the conduction characteristics in LDPE we have carried out the numerical analysis on the basis of experimental results of space charge distribution cathode field and current with time which had been simultaneously measured at applied field of 50kV/mm and room temperature. As the models for numerical analysis we employ the Richarson-Schottky theory for charge injection from electrode into LDPE and the band-tail conduction at crystalline regions and the hopping conduction by traps which mainly exist at the interface regions of crystalline-amorphous region for charge transport in LDPE. Futhermore in order to investigate the influence of physical parameters on the time characteristcs of space charge distribution and measured current we have changed the values of trap density activation energies for charge injection and transport and have analyzed their effects.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1274-1276
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• 1993

The silicon-nitride films formed by laser CVD method are used for passivating GaAs surfaces. The electrical Properties of metal-insulator-GaAs structure are studied to determined the interfacial characteristics by C-V curves and deep level transient spectroscopy(DLTS). The SiN films are photolysisly deposited from $SiH_4\;and\;NH_3$ in the range of $100^{\circ}C-300^{\circ}C$ on P type, (100) GaAs. The hysteresis is reduced and interface trap density is lowered to $10^{12}-10^{13}$ at $100^{\circ}C-200^{\circ}C$. The surface leakage current is studied too. The passivated GaAs have a little leakage current compared to non passivated GaAs.

• 반도체디스플레이기술학회지
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• 제16권2호
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• pp.66-69
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• 2017

In this paper, solution based Indium Zinc Oxide thin film transistors (IZO TFTs) were fabricated with PVP gate dielectric. To enhance the electrical properties, UV-O3 treatment is proposed on solution based IZO TFTs. The gate leakage current and interface trap density is compatible with conventional ZnO-based TFT with inorganic gate insulator. Especially, the UV-treated device shows improved electrical characteristics compared to the untreated device. These results can be explained by X-ray photoelectron spectroscopy (XPS) analysis, which shows that the oxygen vacancy of UV-O3 treatment is higher than that of no treatment.

• 한국전기전자재료학회논문지
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• 제37권1호
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• pp.43-47
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• 2024

The size of semiconductor devices has been scaled down to improve packing density and output performance. However, there is uncontrollable spreading of the dopants that comprise the well, punch-stop, and channel-stop when using high-temperature annealing processes, such as rapid thermal annealing (RTA). In this context, low-temperature deuterium annealing (LTDA) performed at a low temperature of 300℃ is proposed to reduce the thermal budget during CMOS fabrication. The LTDA effectively eliminates the interface trap in the gate dielectric layer, thereby improving the electrical characteristics of devices, such as threshold voltage (V_TH), subthreshold swing (SS), on-state current (I_ON), and off-state current (I_OFF). Moreover, the LTDA is perfectly compatible with CMOS processes.

• 한국전기전자재료학회논문지
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• 제24권12호
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• pp.944-948
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• 2011

In this paper, flicker noise characteristic and channel hot carrier degradation of NMOSFETs with plasma nitrided oixde (PNO) and thermally nitrided oxide (TNO) are analyzed in depth. Compared with NMOSFET with TNO, flicker noise characteristic of NMOSFET with PNO is improved significantly because nitrogen density in PNO near the Si/$SiO_2$ interface is less than that in TNO. However, device degradation of NMOSFET with PNO by channel hot carrier stress is greater than that with TNO although PMOSFET with PNO showed greater immunity to NBTI degradation than that with TNO in previous study. Therefore, concurrent investigation of the reliability as well as low frequency noise characteristics of NMOSFET and PMOSFET is required for the development of high performance analog MOSFET technology.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.193.2-193.2
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• 2016

We evaluate the change in defects in the oxidized SiO2 grown on 4H-SiC (0001) by plasma assisted oxidation, by comparing with that of conventional thermal oxide. In order to investigate the changes in the electronic structure and electrical characteristics of the interfacial reaction between the thin SiO2 and SiC, x-ray photoelectron spectroscopy (XPS), X-ray absorption spectroscopy (XAS), DFT calculation and electrical measurements were carried out. We observed that the direct plasma oxide grown at the room temperature and rapid processing time (300 s) has enhanced electrical characteristics (frequency dispersion, hysteresis and interface trap density) than conventional thermal oxide and suppressed interfacial defect state. The decrease in defect state in conduction band edge and stress-induced leakage current (SILC) clearly indicate that plasma oxidation process improves SiO2 quality due to the reduced transition layer and energetically most stable interfacial state between SiO2/SiC controlled by the interstitial C.

• 전자공학회논문지D
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• 제35D권10호
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• pp.83-90
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• 1998

MOS 캐패시터의 게이트 전극을 비정질 상태의 실리콘으로 형성하여 GOI(Gate Oxide Integrity)특성에 미치는 불순물 활성화 열처리의 효과를 조사하였다. LPCVD(Low Pressure Chemical Vapor Deposition) 방법으로 증착한 비정질 실리콘 게이트 전극은 활성화 열처리에 의하여 다결정 실리콘 상태로 구조가 변화하며, 불순물 원자의 활성화가 충분히 이루어졌다. 또한, 비정질 상태의 게이트 전극은 커다란 압축 응력(compressive stress)을 가지지만, 활성화 열처리 온도가 700℃에서 900℃로 증가함에 따라서 응력이 완화되었고 게이트 전극의 저항도 감소하는 특성을 보였다. 또한 얇은 게이트 산화막의 신뢰성 및 산화막의 계면특성은 활성화 열처리 온도에 크게 의존하고 있었다. 900℃에서 활성화 열처리를 한 경우가 700℃에서 열처리한 경우보다 산화막내에서의 전하 포획 특성이 개선되었으며, 산화막의 신뢰성이 향상되었다. 특히, TDDB 방법으로 예측한 게이트 산화막의 수명은 700℃의 열처리에서는 3×10/sup 10/초였지만, 900℃에서의 열처리에서는 2×10/sup 12/초로 현저하게 개선되었다. 그리고, 산화막 계면에서의 계면 전하 밀도는 게이트의 응력 완화에 따라서 개선되었다.

• 센서학회지
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• 제29권4호
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• pp.266-269
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• 2020

In this study, we investigated the effect of a sulfur passivation (S-passivation) process step on the electrical properties of surface-channel In_0.7Ga_0.3As quantum-well (QW) metal-oxide-semiconductor field-effect transistors (MOSFETs) with S/D regrowth contacts. We fabricated long-channel In_0.7Ga_0.3As QW MOSFETs with and without (NH₄)₂S treatment and then deposited 1/4 nm of Al₂O₃/HfO₂ through atomic layer deposition. The devices with S-passivation exhibited lower values of subthreshold swing (74 mV/decade) and drain-induced barrier lowering (19 mV/V) than the devices without S-passivation. A conductance method was applied, and a low value of interface trap density D_it (2.83×10¹² cm^-2eV^-1) was obtained for the devices with S-passivation. Based on these results, interface traps between InGaAs and high-κ are other defect sources that need to be considered in future studies to improve III-V microsensor sensing platforms.

• The Korean Journal of Ceramics
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• 제6권2호
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• pp.138-142
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• 2000

Thin film $LiNbO_3$MFS (metal-ferroelectric-semiconductor) capacitor showed improved characteristics such as low interface trap density, low interaction with Si substrate, and large remanent polarization. This paper reports ferroelectric $LiNbO_3$thin films grown directly on p-type Si (100) substrates by 13.56 MHz RF magnetron sputtering system for FRAM (ferroelectric random access memory) applications. RTA (rapid thermal anneal) treatment was performed for as-deposited films in an oxygen atmosphere at $600^{\circ}C$ for 60sec. We learned from X-ray diffraction that the RTA treated films were changed from amorphous to poly-crystalline $LiNbO_3$which exhibited (012), (015), (022), and (023) plane. Low temperature film growth and post RTA treatments improved the leakage current of $LiNbO_3$films while keeping other properties almost as same as high substrate temperature grown samples. The leakage current density of $LiNbO_3$films decreased from $10^{-5}$ to $10^{-7}$A/$\textrm{cm}^2$ after RTA treatment. Breakdown electric field of the films exhibited higher than 500 kV/cm. C-V curves showed the clockwise hysteresis which represents ferroelectric switching characteristics. Calculated dielectric constant of thin film $LiNbO_3$illustrated as high as 27.9. From ferroelectric measurement, the remanent polarization and coercive field were achieved as 1.37 $\muC/\textrm{cm}^2$ and 170 kV/cm, respectively.