• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.9
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• pp.46-55
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• 1992

This paper propose how to calculate the capacitance for VLSI interconnection lines in multi-dielectric layer. The proposed method is a expansive form of 3-dimensional direct intergral method developed in single-dielectric layer. We took into consideration the effect of multi-dielectric layer by using additional boundary condition instead of modified Green's function. It is used the potential equations in line surface and the electric field equations in dielectric interface as the boundary condition. RC delay time for interconnection line of multi-dielectric layer is obtained from the calculated capacitance value. At this time, we are used Al and WSiS12T as interconnection materials.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.8
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• pp.1-10
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• 2001

This paper describes new line code algorithm, called NIDI(Nibble Inversion mock Inversion) which is well suited for interconnection and transmission technology, The proposed line code which includes only one redundancy bit serves primary features of line code and synchronization patterns for byte or frame synchronization in interconnection, Also, this line code provides in-band signals and speciaI characters.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.8
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• pp.1187-1196
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• 1989

In this paper, a method for computing the capacitance parameter for a multi-interconnection line in a multilayered dielectric region is presented. The number of interconnection lines and the number of dielectric layers are arbitrary, and the interconnection lines are finite cross section or infinite cross section. The surface of lines and dielectric interface are divided into subsection. The surface charge density of each subsection is a constant step-pulse function for each subsection. After the solution of surface charge density is effected by the method of moments, capacitance parameter is calculated.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.7 no.5
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• pp.395-407
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• 1996

In this paper, we describe the crossover of the parasitic capacitance at the interconnections for the system miniature, analyse ground capacitance and mutual capacitance due to actually coupled line in the ICs or MCMs. From the results of deviding interconnection line with infinite parts, using Green's function with image charge method and moments, we could obtain 70% decrease of system runtime parasitic inductance because of simplicity of transforming formular.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.7
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• pp.1129-1134
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• 2008

This paper proposes a reliability evaluation for interconnection planning using a tie line equivalent assisting generator model (TEAG) that considers the uncertainties of the interconnected transmission systems and the tie lines. Development of this model was triggered by the need to perform probabilistic reliability evaluations on the NEAREST (North East Asia Region Electric Systems Tied) interconnection. The TEAG is the basis for the newly developed interconnection systems reliability evaluation computer program, NEAREL. The model is capable of considering uncertainties associated with generators, tie lines, and the tied grids. Reliability evaluations for six interconnection scenarios involving the power systems of six countries in the Asian north eastern region were performed using NEAREL. Sensitivity analysis was used to determine reasonable tie line capacities for three interconnected country scenarios of the six countries. Test results and summarized comments of the scenarios are included in the paper.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.545-552
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• 2008

It becomes to make its necessity of getting more closer approach for the design and the detailed analysis of implementation method and study with respect that the plan is put into shape for the interconnection between Seoul Line No.9 and the AREX line which has been on commercial running since it had been opened on March 2007. We introduce the concrete analysis and the rasied problems and a way how to solve as well for the characteristics of interconnection train and signaling 시스템tem structure between two lines in order to design and implement the interconnection running. Also,

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.4
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• pp.435-442
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• 2004

This paper presents a hermetic MEMS on-chip package bonded by a closed-loop AuSn solder-line. We design three different package specimens, including a substrate heated specimen without interconnection-line (SHX), a substrate heated specimen with interconnection-line (SHI) and a locally heated specimen with interconnection-line (LHI). Pressurized helium leak test has been carried out for hermetic seal evaluation in addition to the critical pressure test for bonding strength measurement. Substrate heating method (SHX, SHI) requires the bonding time of 40min. at 400min, while local heating method (LHI) requires 4 min. at the heating power of 6.76W. In the hermetic seal test. SHX, SHI and LHI show the leak rates of 5.4$\pm$6.7${\times}$$^{-10}$ mbar-l/s, 13.5$\pm$9.8${\times}$$^{-10}$ mbar-l/s and 18.5$\pm$9.9${\times}$$^{-10}$ mbar-l/s, respectively, for an identical package chamber volume of 6.89$\pm$0.2${\times}$$^{-10}$. In the critical pressure test, no fracture is found in the bonded specimens up to the applied pressure of 1$\pm$0.1MPa, resulting in the minimum bonding strength of 3.53$\pm$0.07MPa. We find that the present on-chip packaging using a closed AuSn solder-line shows strong potential for hermetic MEMS packaging with interconnection-line due to the hermetic seal performance and the shorter bonding time for mass production.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.30 no.4 s.247
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• pp.373-378
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• 2006

We present the design, fabrication, and characterization of a multi-chip microelectrofluidic bench, achieving both electrical and fluidic interconnections with a simple, low-loss and low-temperature electrofluidic interconnection method. We design 4-chip microelectrofluidic bench, having three electrical pads and two fluidic I/O ports. Each device chip, having three electrical interconnections and a pair of two fluidic I/O interconnections, can be assembled to the microelectofluidic bench with electrical and fluidic interconnections. In the fluidic and electrical characterization, we measure the average pressure drop of $13.6{\sim}125.4$ Pa/mm with the nonlinearity of 3.1 % for the flow-rates of $10{\sim}100{\mu}l/min$ in the fluidic line. The pressure drop per fluidic interconnection is measured as 0.19kPa. Experimentally, there are no significant differences in pressure drops between straight channels and elbow channels. The measured average electrical resistance is $0.26{\Omega}/mm$ in the electrical line. The electrical resistance per each electrical interconnection is measured as $0.64{\Omega}$. Mechanically, the maximum pressure, where the microelectrofluidic bench endures, reaches up to $115{\pm}11kPa$.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.9
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• pp.83-88
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• 2014

When DG interconnection into network is examined, details of the review are overvoltage, protective device malfunction, etc. In the case of protective device malfunction, replacing protective device into bi-directional protective device and installation NGR are the solution. Overvoltage at interconnection point occurs because the load is relatively less than DG output. When overvoltage at interconnection point occurs, DG interconnection is not permitted because this overvoltage affect other customers. Interconnection by installation new distribution line is one solution but it costs much money. Without installation new investment, change of NOP(Normal Open Point) position is a possible solution about DG interconnection into network.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.3
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• pp.302-307
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• 1988

A noble interconnection line capacitance measurement method to be able to remove the measurement errors from the probe pad to substrate stray capacitance has been proposed and verified. The measurement errors in the capacitance measurement, which usually be involved from the probe pad to substrate stray capacitance, can easily be removed by isolating the metal probe pad from the substrate with a grounded shield plate between the probe pad the substrate. The measurement results by using this improved capacitance measurement method were compared with the calculations by two-dimensional computer simulations.