• 전자공학회논문지A
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• 제29A권9호
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• pp.46-55
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• 1992

본 논문에서는 다층유전체 구조를 갖는 VLSI interconnection line 에 대한 커페시턴스를 계산하기 위한 방법을 제안한다. 이 방법은 단일 유전체 구조에서 개발한 3차원 직접 적분방법을 확장한 것이다. 다층유전체에 의한 영향은 Green's function을 수정하는 대신에 경계조건을 추가함으로써 고려하였다. 여기서 사용한 경계조건은 line 표면에서는 전위에 대한 식을 사용하였고, 유전체 경계면ㅇ서는 전계에 대한 식을 사용하였다. 이 방법으로부터 얻어진 커패시턴스를 이용하여 다층유전체 구조에서의 interconnection line에 대한 RC 지연시간의 값을 구했다. 이때 사용한 interconnection 물질은 Al과 WSi-이다.

• 대한전자공학회논문지TC
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• 제38권8호
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• pp.1-10
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• 2001

본 논문에서는 전송 분야 뿐만 아니라 interconnection 분야에서 사용할 수 있는 새로운 선로 부호를 제안한다. 제안된 선로 부호는 1 비트의 잉여(redundancy) 비트를 사용하면서도 선로 부호가 갖는 기본적인 특징을 보장하며, interconnection 분야에서 필요한 byte 또는 frame 동기를 위한 직렬 동기 패턴 제공, 특수 문자 또는 in-band signaling을 제공한다. 8비트 이상의 병렬 데이터를 부호화 하거나 직렬 비트 스트림(steam)으로 전송하기 쉽게 하여 주는 제안된 NIBI 부호 생성 알고리즘, 복호 알고리즘 및 부호 성능에 대해서 기술한다.

• 대한전자공학회논문지
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• 제26권8호
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• pp.1187-1196
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• 1989

In this paper, a method for computing the capacitance parameter for a multi-interconnection line in a multilayered dielectric region is presented. The number of interconnection lines and the number of dielectric layers are arbitrary, and the interconnection lines are finite cross section or infinite cross section. The surface of lines and dielectric interface are divided into subsection. The surface charge density of each subsection is a constant step-pulse function for each subsection. After the solution of surface charge density is effected by the method of moments, capacitance parameter is calculated.

• 한국전자파학회논문지
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• 제7권5호
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• pp.395-407
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• 1996

In this paper, we describe the crossover of the parasitic capacitance at the interconnections for the system miniature, analyse ground capacitance and mutual capacitance due to actually coupled line in the ICs or MCMs. From the results of deviding interconnection line with infinite parts, using Green's function with image charge method and moments, we could obtain 70% decrease of system runtime parasitic inductance because of simplicity of transforming formular.

• 전기학회논문지
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• 제57권7호
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• pp.1129-1134
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• 2008

This paper proposes a reliability evaluation for interconnection planning using a tie line equivalent assisting generator model (TEAG) that considers the uncertainties of the interconnected transmission systems and the tie lines. Development of this model was triggered by the need to perform probabilistic reliability evaluations on the NEAREST (North East Asia Region Electric Systems Tied) interconnection. The TEAG is the basis for the newly developed interconnection systems reliability evaluation computer program, NEAREL. The model is capable of considering uncertainties associated with generators, tie lines, and the tied grids. Reliability evaluations for six interconnection scenarios involving the power systems of six countries in the Asian north eastern region were performed using NEAREL. Sensitivity analysis was used to determine reasonable tie line capacities for three interconnected country scenarios of the six countries. Test results and summarized comments of the scenarios are included in the paper.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2008년도 춘계학술대회 논문집
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• pp.545-552
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• 2008

2007년 3월에 1단계 구간이 개통되어 운영 중에 있는 공항철도와 서울시 지하철9호선의 직결운행에 대한 계획이 구체화되어감에 따라 구현방안에 대한 상세한 검토와 함께 설계에 대한 보다 체계적인 접근이 요구되고 있다. 본 논문에서는 직결운행을 위해 요구되는 신호시스템의 체계와 이에 따른 직결운행 전동차의 특성 등에 대해 구체적인 분석과 함께 문제점 및 해결방안 등을 제시한다. 또한, 신호시스템 분야에서 바라 본 공항철도와 서울9호선의 물리적인 특성과 운영방식에 따라 기존 시스템의 수정사항 및 직결을 위해 새로이 구현되어야 할 사항들에 대해 구체적으로 살펴보고 기존의 직결운행 사례에 비해 본 직결운행이 갖고 있는 특징과 요구조건 들에 대해 보다 구체적이고 체계적인 접근을 시도하여 직결구현의 방안 및 기본기준을 제시하여 향후 직결구현에 대한 지침으로 활용될 수 있도록 한다.

• 대한기계학회논문집A
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• 제28권4호
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• pp.435-442
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• 2004

This paper presents a hermetic MEMS on-chip package bonded by a closed-loop AuSn solder-line. We design three different package specimens, including a substrate heated specimen without interconnection-line (SHX), a substrate heated specimen with interconnection-line (SHI) and a locally heated specimen with interconnection-line (LHI). Pressurized helium leak test has been carried out for hermetic seal evaluation in addition to the critical pressure test for bonding strength measurement. Substrate heating method (SHX, SHI) requires the bonding time of 40min. at 400min, while local heating method (LHI) requires 4 min. at the heating power of 6.76W. In the hermetic seal test. SHX, SHI and LHI show the leak rates of 5.4$\pm$6.7${\times}$$^{-10}$ mbar-l/s, 13.5$\pm$9.8${\times}$$^{-10}$ mbar-l/s and 18.5$\pm$9.9${\times}$$^{-10}$ mbar-l/s, respectively, for an identical package chamber volume of 6.89$\pm$0.2${\times}$$^{-10}$. In the critical pressure test, no fracture is found in the bonded specimens up to the applied pressure of 1$\pm$0.1MPa, resulting in the minimum bonding strength of 3.53$\pm$0.07MPa. We find that the present on-chip packaging using a closed AuSn solder-line shows strong potential for hermetic MEMS packaging with interconnection-line due to the hermetic seal performance and the shorter bonding time for mass production.

• 대한기계학회논문집A
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• 제30권4호
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• pp.373-378
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• 2006

We present the design, fabrication, and characterization of a multi-chip microelectrofluidic bench, achieving both electrical and fluidic interconnections with a simple, low-loss and low-temperature electrofluidic interconnection method. We design 4-chip microelectrofluidic bench, having three electrical pads and two fluidic I/O ports. Each device chip, having three electrical interconnections and a pair of two fluidic I/O interconnections, can be assembled to the microelectofluidic bench with electrical and fluidic interconnections. In the fluidic and electrical characterization, we measure the average pressure drop of $13.6{\sim}125.4$ Pa/mm with the nonlinearity of 3.1 % for the flow-rates of $10{\sim}100{\mu}l/min$ in the fluidic line. The pressure drop per fluidic interconnection is measured as 0.19kPa. Experimentally, there are no significant differences in pressure drops between straight channels and elbow channels. The measured average electrical resistance is $0.26{\Omega}/mm$ in the electrical line. The electrical resistance per each electrical interconnection is measured as $0.64{\Omega}$. Mechanically, the maximum pressure, where the microelectrofluidic bench endures, reaches up to $115{\pm}11kPa$.

• 조명전기설비학회논문지
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• 제28권9호
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• pp.83-88
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• 2014

When DG interconnection into network is examined, details of the review are overvoltage, protective device malfunction, etc. In the case of protective device malfunction, replacing protective device into bi-directional protective device and installation NGR are the solution. Overvoltage at interconnection point occurs because the load is relatively less than DG output. When overvoltage at interconnection point occurs, DG interconnection is not permitted because this overvoltage affect other customers. Interconnection by installation new distribution line is one solution but it costs much money. Without installation new investment, change of NOP(Normal Open Point) position is a possible solution about DG interconnection into network.

• 대한전자공학회논문지
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• 제25권3호
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• pp.302-307
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• 1988

A noble interconnection line capacitance measurement method to be able to remove the measurement errors from the probe pad to substrate stray capacitance has been proposed and verified. The measurement errors in the capacitance measurement, which usually be involved from the probe pad to substrate stray capacitance, can easily be removed by isolating the metal probe pad from the substrate with a grounded shield plate between the probe pad the substrate. The measurement results by using this improved capacitance measurement method were compared with the calculations by two-dimensional computer simulations.