• Information and Communications Magazine
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• v.11 no.4
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• pp.62-70
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• 1994

This paper discusses the LAN interface technics physically applicable to the ISDN exchange system through frame relay without changing of the basic exchange architecture. To ensure the success of frame relaying, it's interworking with the existing X.25 services is very imported, and for this purpose both X.75 and 1.122-based interworking alternative must be considered. Definition required to frame relay, interconnection of remote bridge and ways to design the Frame Handler carrying a frame realying in the ISDN node was introduced here. Subsequently, alternatives using the X.25 and X.75 or 1.122 as well as interconnection mechanism LAN and ISDN for the LAN interface and LAN and/or LAN interface and ISDN through frame relay was individually introduced. Through frame relay applications in the major countries, the achievement of high speed frame relaying service to the LAN was introduced.

• Journal of Information Processing Systems
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• v.14 no.1
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• pp.270-279
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• 2018

PCI Express (PCIe) bus, which was only used as an internal I/O bus of a computer system, has expanded its function to outside of a system, with progress of PCIe switching processor. In particular, advanced features of PCIe switching processor enable PCIe bus to serve as an interconnection network as well as connecting external devices. As PCIe switching processors more advanced, it is required to consider the different adapter card architecture. This study developed multipurpose adapter cards by applying an on-board optical module, a latest optical communications element, in order to improve transfer distance and utilization. The performance evaluation confirmed that the new adapter cards with long cable can provide the same bandwidth as that of the existing adapter cards with short copper cable.

• Journal of information and communication convergence engineering
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• v.19 no.2
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• pp.114-119
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• 2021

This paper proposes a method to find an optimal T' with the most terminal of the subset of T' trees that can be connected by a given length by improving a memetic genetic algorithm within several constraints, when the set of terminal T is given to the Euclidean plane R². Constraint (1) is that a given length cannot connect all terminals of T, and (2) considers only the rectilinear layout of the edge connecting each terminal. The construction of interconnections has been used in various design-related areas, from network to architecture. Among these areas, there are cases where only the rectilinear layout is considered, such as wiring paths in the computer network and VLSI design, network design, and circuit connection length estimation in standard cell deployment. Therefore, the heuristics proposed in this paper are expected to provide various cost savings in the rectilinear layout.

• Journal of information and communication convergence engineering
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• v.20 no.2
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• pp.90-95
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• 2022

This paper proposes a method to find a tree with the maximum number of terminals that can be connected by a given length when numerous terminals distributed in a cluster form are given to the Euclidean plane R2 with several constraints. First constraint is that a given terminal is distributed in a cluster form, second is that a given length cannot connect all terminals in the tree, and third is that there is no curved connection between each terminal. This paper proposes a method to establish more efficient interconnections within terminals distributed in a cluster form by improving a randomly distributed memetic genetic algorithm. The construction of interconnections has been extensively used in design-related fields, from networking to architecture. Additionally, in real life, the construction of interconnections is mostly distributed in the form of clusters. Therefore, the heuristic algorithm proposed in this paper can be effectively utilized in real life and is expected to provide various cost savings.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.155-164
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• 1996

The architecture of a programmable video codec IC is described that employs multiple vector processors in a single chip. The vector processors operate in parallel and communicate with one another through on-chip shared memories. A single scalar control processor schedules each vector processor independently to achieve real-tiem video coding with special vector instructions. With programmable interconnection buses, the proposed architecture performs multi-processing of tasks and data in video coding. Therefore, it can provide good parallelism as well as good programmability. especially, it can operate multithread video coding, which processes several independent image sequences simultaneously. We explain its scheduling, multithred video coding, and vector processor architectures. We implemented a prototype video codec with a 0.8um CMOS cell-based technology for the multi-standard videophone. This codec can execute video encoding and decoding simultaneously for the QCIF image at a frame rate of 30Hz.

• Journal of Broadcast Engineering
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• v.4 no.2
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• pp.134-143
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• 1999

In this paper, in order to implement the IDWT(inverse discrete wavelet transform) with relatively low complexity, we propose a VLSI architecture for odd-tap linear-phase IDWT filters. By considering the symmetric property of the linear phase filter, the input is added to the one located at symmetrical position of the filter before filtering. Then. we rearrange the delay line of the filter in a U-shaped fashion. requiring no global interconnection between the components. The proposed architecture for the IDWT filter consists of delay units. operator units, adder units. and postprocessor unit. Since each units are configured regularly and interconnected locally. the proposed architecture can accommodate arbitrary linear phase IDWTs by simply adding/removing the corresponding units. The M -level IDWT can be implemented by interconnecting the proposed architecture in a cascaded or semi-recursive form. It is expected that the proposed architecture for the IDWT can be effectively employed in the related area including MPEG-4, since the proposed architecture is less complex than the conventional architectures.

• Journal of the Korea Society of Computer and Information
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• v.16 no.6
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• pp.1-10
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• 2011

In designing multi-core processors, interconnection delay is one of the major constraints in performance improvement. To solve this problem, the 3-dimensional integration technology has been adopted in designing multi-core processors. The 3D multi-core architecture can reduce the physical wire length by stacking cores vertically, leading to reduced interconnection delay and reduced power consumption. However, the power density of 3D multi-core architecture is increased significantly compared to the traditional 2D multi-core architecture, resulting in the increased temperature of the processor. In this paper, the floorplan methods which change the forms of vertical placement of the core and the level-2 cache are analyzed to solve the thermal problems in 3D multi-core processors. According to the experimental results, it is an effective way to reduce the temperature in the processor that the core and the level-2 cache are stacked adjacently. Compared to the floorplan where cores are stacked adjacently to each other, the floorplan where the core is stacked adjacently to the level-2 cache can reduce the temperature by 22% in the case of 4-layers, and by 13% in the case of 2-layers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.91-103
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• 2002

For massive FPGA based emulator, the interconnection architecture and the transmission method of signals between FPGA's are important elements which decide speed of emulation and extendability of emulator. Existing FPGA-based emulation system is faced the problems of which the emulation speed getting slow drastically as the complexity of circuit increases. In this paper, we proposed a new innovative emulation architecture that has high resource usage rate and makes the fast emulation Possible. The emulator with very unique hierarchical ring topology Presented here has merits to overcome FPGA pin limitation by connecting each FPGA into a set of pipelined rings, and it also makes emulation speed at the tens of MHz at least even at system level where the verification complexity can easily exceed the verification capability of designers.

• Proceedings of the Korea Contents Association Conference
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• 2009.05a
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• pp.642-647
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• 2009

We proposed the method of avionics integrated architecture using high-speed fiber optic bus. Typically, data bus of aircraft consists of electronic and optic data transmission method. Avionics systems are difficult to operate the electronic data transmission method for the high speed data processing, synchronization and interconnection between flight control system and flight management system efficiently. In this paper, it is known to look into the problem of data bus and the advanced trend in avionics systems, and propose the appropriate data bus of the advanced avionics systems.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.140-151
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• 1996

In this study, we designed the routing structure and logic block of a SRAM cell-based FPGA with symmetrical-array architecture. The designed routing structure is composed of switch matrices, routing channels and I/O blocks, and the routing channels can be subdivided into single length channels, double length channels and global length channels. The interconnection between wires is made through SRAM cell-controlled pass transistors. To reduce the signal delay in pass transistors, we proposed a scheme raising the gate-control voltage to 7V. The designed SRAM cells have built-in shift register capability, so there is no need for separate shift registers. We designed SRAM cells in the LUTs(look-up tables) to enable the wirte operations to be performed synchronously with the clock for ease of system application. Each logic block (LFU) has four 4-input LUTs, flip-flops and other gates, and the LUTs can be used a sSRAM memory. The LFU also has a dedicated carry logic, so a 4-bit adder can be implemented in one LFU. We designed our FPGA using 0.6.mu.m CMOS technology, and simulation shows proper operation of a 4 bit counter at 100MHz.