Browse > Article

REGO: REconfiGurable system emulatOr  

Kim, Nam-Do (Dept.of Computer Science Engineering, Busan National University)
Yang, Se-Yang (Dept.of Computer Science Engineering, Busan National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.39, no.2, 2002 , pp. 91-103 More about this Journal
Abstract
For massive FPGA based emulator, the interconnection architecture and the transmission method of signals between FPGA's are important elements which decide speed of emulation and extendability of emulator. Existing FPGA-based emulation system is faced the problems of which the emulation speed getting slow drastically as the complexity of circuit increases. In this paper, we proposed a new innovative emulation architecture that has high resource usage rate and makes the fast emulation Possible. The emulator with very unique hierarchical ring topology Presented here has merits to overcome FPGA pin limitation by connecting each FPGA into a set of pipelined rings, and it also makes emulation speed at the tens of MHz at least even at system level where the verification complexity can easily exceed the verification capability of designers.
Keywords
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 Bondyopadhyay, P. K. 'Moore's law governs the silicon revolution', Proc. of the IEEE, Vol.86, Issue.1, pp. 78-81, Jan. 1988   DOI   ScienceOn
2 B.S. Landman and R.L. Russo. 'On a pin versus block relationship for partitions of analogic graphs', IEEE Trans. on Computer, Vol.C-20, pp. 1469-1479, 1971   DOI   ScienceOn
3 Jonathan Babb, Russel Tessier, Matthew Dahl, Silvian Zimi Hanono, David M Hoki, and Anant Agarwal, 'Logic Emulator with Virtual Wires', IEEE Trans. on CAD, Vol.16, No.6, pp. 609-626, June 1994   DOI   ScienceOn
4 Quickturn Design System, Inc., 'Emulation System with time-multiplexed interconnect', US patent 005960191, May 30 1997
5 Verplaetse. P, 'Refinements of rent's rule allowing accurate interconnect complexity modeling', 2001 International Symposium on Quality Electronic Design, pp. 251-252, 2001   DOI
6 Chih-Chang Lin, Chang. D, Yu-Liang Wu, Marek-Sadowska. M, 'Time-Multiplexed Routing for FPGA design', in Proc. 1996 ACM Int. Workshop on Field-Programmable Gate Arrays, pp. 152-155, Feb. 1996   DOI
7 Robert A. Walker, Raul Camposano. A survey of high-level synthesis systems, Kluwer Academic Publishers, pp. 16-17, 1991
8 Xilinx Databook 2001 http://www.xilinx.com/partinfo/databook.htm
9 Hauck. S, Borriello. G, Ebeling. C, 'Mesh routing topologies for multi-fpga systems', IEEE Trans. on VLSI systems, Vol.6, No.3, pp. 400-408, Sept. 1998   DOI   ScienceOn
10 Jonathan Babb, Russel Tessier, and Anant Agarwal, 'Virtual wires: Overcoming pin limitations in FPGA-based logic emulators', in Proc. IEEE workshop FPGA-based custom computing machines, pp. 142-151, April 1993   DOI
11 S.Matic, 'Emulation of hypercube architecture on nearest-neighbor mesh-connected processing elements', IEEE Trans. on Computer, Vol.39. pp. 698-700, May 1990   DOI   ScienceOn
12 Jianmin Li, Chung-Kuan Cheng, 'Routability improvement using dynamic interconnect architecture', IEEE Trans. on Very Large Scale Integration (VLSI) Systems, Vol.6, Issue.3, pp. 498-501, Sept 1998   DOI   ScienceOn
13 D. Jones and D. Lewis, 'A time multipelxed FPAG architecture for logic emulation', in Proc. 3rd Canadian workshop on Field-programmable devices, pp. 495-498, May 1995
14 Joseph Varghese, Michael Butts, and Jon Batcheller, 'An Efficient logic emulation system', IEEE Trans. on VLSI systems, Vol.1, No.2, pp. 171-174, June 1933   DOI   ScienceOn
15 Courtoy, M. 'Rapid system prototyping for real-time design validation', in Proc. 1988 Ninth Int. Workshop on Rapid System Prototyping, pp. 108-112, 1998
16 Hsiao-Pin Su and Youn-Long Lin, 'A Phase assignment method for virtual-wire-based hardware emulation', IEEE Trans. on CAD of IC and system, Vol.16, No.7, pp. 776-783, July 1997   DOI   ScienceOn