• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.265-274
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• 2010

As the process technology scales down and integration densities continue to increase, interconnection has become one of the most important factors in performance of recent multi-core processors. Recently, to reduce the delay due to interconnection, 3D architecture has been adopted in designing multi-core processors. In 3D multi-core processors, multiple cores are stacked vertically and each core on different layers are connected by direct vertical TSVs(through-silicon vias). Compared to 2D multi-core architecture, 3D multi-core architecture reduces wire length significantly, leading to decreased interconnection delay and lower power consumption. Despite the benefits mentioned above, 3D design technique cannot be practical without proper solutions for hotspots due to high temperature. In this paper, we propose three floorplan schemes for reducing the peak temperature in 3D multi-core processors. According to our simulation results, the proposed floorplan schemes are expected to mitigate the thermal problems of 3D multi-core processors efficiently, resulting in improved reliability. Moreover, processor performance improves by reducing the performance degradation due to DTM techniques. Power consumption also can be reduced by decreased temperature and reduced execution time.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.209-212
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• 2000

This paper discusses performance evaluation methodologies for wired/wireless Ethernet adaptors. This paper defines test cases for performance evaluation of LAN adaptor and its environments. Performance evaluation of LAN adaptor is mote complex as compared with interconnection devices such as Ethernet HUB and Ethernet switch, because its performance depends on the system on which the adaptor is plugged. Such dependencies include CUP type, RAM size, system bus architecture(PCI bus clock), etc.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.122-134
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• 1994

Design of a heuristic algorithm for high level synthesis of multichip architecture is presented in this paper. Considering the design constraints: individual chip area, I/O pin counts, chip-to-chip interconnection counts, interchip communication delay, and chip latecy, the proposed system automatically generates pipelined multichip architectures from behavioral descriptions. For efficient mulichip synthesis, a new methodology is proposed, which performs partitioning and schedulting of SFG into multichip architectures simultaneously. Experimental results for several benchmark programs show that the systems can be used for designing multichip hardware efficiently.

• KIEAE Journal
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• v.13 no.6
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• pp.17-22
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• 2013

Community has been defined as a group of interacting people living in a common location. The word is often used to refer to a group that is organized around common values and is attributed with social cohesion within a shared geographical location, generally in social units larger than a household. The word can also refer to the national community or global community. The word "community" is derived from the Old French communit$\acute{e}$ which is derived from the Latin communitas (cum, "with/together" + munus, "gift"), a broad term for fellowship or organized society. A sense of community refers to people's perception of interconnection and interdependence, shared responsibility, and common goals. Understanding a community entails having knowledge of community needs and resources, having respect for community members, and involving key community members in programs. But, on account of industrial development, At some point, we have individualism behavior. therefore, This study will achieve local community activation using school land.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.291-294
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• 2001

This Current research for software architecture views and models a software system as a set of components and connectors. Components are ions of system level computational entities, connectors are ions of component interrelationships. In his paper, we focus attention on connectors for the Java Beans-based systems that are built using object integration technologies like CORBA. We present connector model in lava Beans-based system for object-oriented component integration. We start with a discussion of related work of software architecture research and of Object-Oriented modeling that focuses on the description of component collaborations. We propose connectors as transferable ions of system level component interconnection and inter-operation. Connectors are architectural ions of component coordination in the architecture of a system only. Connectors describe a collaboration rationale for component adaptations, which are then modeled in the concrete architecture of a system.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.4
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• pp.10-21
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• 2003

Recently, the optical subscriber interface module uses the high performance network processor to quickly develop new application services such as MPLS, VPN, RPR and EPON with a short time-to-market. Although a number of vendors are developing the network processor at 2.5Gbps, only the IBM NP4GS3 can provide packet processing with wire-speed at 2.5Gbps. IBM NP4GS3, however, uses its unique speed DASL interface instead of CSIX-Ll interface, which has standardized by M: Forum currently Therefore, we implement an interconnection mechanism to use the switch fabric with CSIX-Ll interface. In this paper, we suggest the architecture and a packet control mechanism supporting interconnection between IBM NP4GS3 DASL and CSIX-Ll switch interface using the common IBM UDASL ASIC and XILINX FPGA.

• The Transactions of the Korea Information Processing Society
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• v.3 no.4
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• pp.961-968
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• 1996

In the frame of Koreasat Project, it has been identified the task to implement a pilot satellite network module to provide LAN-to-LAn in ground system for satellite links. The pilot network will support an experiment to verify the performances of the considered applications through a satellite.This paper proposes a satellite-LAN interconnecting architecture making full use of satellite benefits and counteracting satellite demerits. The architectureprovides high quality data transmission and high perfrmance for satellite bit errors by using a connection- oriented satellite protocol which can establish multiple logical links between two nodes. As a protocol conversion method, router-type interconnection was selected to guard against problems. Based on this architecture, a satellite LAN interconnecting system has been designed, which includes a 1.8 meter antenna with a 4 watt transceiver, a satellite modem and the developed satellite network interface. The system can support high speed transmission rates of up to 1.544 Mbs and superior network management as well.

• Journal of IKEEE
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• v.17 no.2
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• pp.168-175
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• 2013

The delay times due to the propagating of data on PCB depend on the shape and length of interconnection lines when memory controllers and high speed memories are soldered on the PCB. The dependency on the placement and routing on the PCB requires redesign of I/O logic or reconfiguration of the memory controller after the delay time is measured if the controller is programmable. In this paper, we propose architecture of configuring logic for the delay time estimation by writing and reading test patterns while initializing the memories. The configuration logic writes test patterns to the memory and reads them by changing timing until the correct patterns are read. The timing information is stored and the configuration logic configures the memory controller at the end of initialization. The proposed method enables easy design of systems using PCB by solving the problem of the mismatching caused by the variation of placement and routing of components including memories and memory controllers. The proposed method can be applied to high speed SRAM, DRAM, and flash memory.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.10
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• pp.1190-1196
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• 2016

In this paper, a cross-layer interworking scheme for different protocols is proposed to provide an efficient internet services in very small aperture terminal (VSAT) based satellite communication systems. In addition, we implement the proposed interworking model and prove the feasibility of the proposed system. VSAT based satellite communication systems commonly use digital video broadcasting (DVB)-S2 standard. Unfortunately, DVB-S2 has inefficient parts to support IP based internet services because it has originally been designed to support broadcasting services. Generic stream encapsulation (GSE) protocol, which is a layer 2 protocol, has been proposed to mitigate this inefficiency. We propose a cross-layer interworking scheme to cooperate efficiently between IP and GSE protocols and between GSE protocol and DVB-S2, respectively. In addtion, we implement the proposed interworking schemes via computer softwares and prove the feasibility using NI-USRP and commercial DVB receiver.

• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1027-1036
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• 1996

X.500 Directory is an application level protocol in the Open Systems Interconnection(OSI) 7 layer's reference model adopted by the international Standards Organization (ISO). It manages effectively needed information for the communication service, and is a service to support the functions that the user can approach conveniently. Tourist information is distribution on several locations. The access of distributed information is similar to X.500 directory service. Therefore, we design of Tourist Information System(TIS) and directory schema using X.500 directory services. To define tourist information, we also propose Directory Information Tree(DIT) of locality architecture and several new object classes, such as museum, mountain, sea, hotel, etc.