• Journal of KIISE
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• v.42 no.5
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• pp.551-557
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• 2015

The technology using ARM TrustZone draws attention as a new embedded virtualization approach. The ARM TrustZone defines two virtual execution environment, the secure world and the normal world. In such an environment, the inter-world communication is important to extend function of software. However, the current monitor software does not sufficiently support the inter-world communication. This paper presents a new inter guestOS communication scheme, for each world, for the ARM TrustZone virtualization. The proposed communication scheme supports bidirectional inter-world communication for single core and multicore environment. In this paper, It is implemented on a NVIDIA Tegra3 processor based on the ARM Cortex-A9 MPCore and it showed a bandwidth of 30MB/s.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.9
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• pp.1202-1208
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• 1995

Inter-processor communication is required to manage resources in ATM switching system where processors are distributed. ATM switching system, which was developed in our institute, does't have dedicated communication path for inter-processor communication, but use the ordinary switching network same as user data. Therefore, we should test communication paths and equipments before running various application software programs. In this paper, we propose a method to test communication paths between processors in ATM switching system and describe an implemented program using this method.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.5
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• pp.590-597
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• 2002

Currently, with the increasing demand for combining cellular phone and PDA, various kinds of PDA-phones are being developed. A typical PDA-phone consists of a CDMA processor and a PDA processor. Generally, a UART serial communication port is used for inter-processor communication. However, the CDMA standard will need more data bandwidth over 2Mbps with the emergence of IMT-2000. The bandwidth requirement is beyond the capability of UART. In this paper, several inter-processor communication mechanisms are analyzed and especially Dual Port Memory and USB were chosen as the candidates for the new communication mechanism. A prototype PDA-phone board has been implemented for experiment. The experimental result shows that Dual Port Memory is better than USB in cost performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.2043-2052
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• 1994

This paper proposes a new parallel ASIC architecture for real-time image processing to reduce inter-processing element (inter-PE) communication overhead, called a Sliding Memory Plane (SliM) Image Processor. The Slim Image Processor consists of $3\times3$ processing elements (PEs) connected by a mesh topology. With easy scalability due to the topology. a set of SliM Image Processors can form a mesh-connected SIMD parallel architecture. called the SliM Array Processor. The idea of sliding means that all pixels are slided into all neighboring PEs without interrupting PEs and without a coprocessor or a DMA controller. Since the inter-PE communication and computation occur simultaneously. the inter-PE communication overhead, significant disadvantage of existing machines greatly diminishes. Two I/O planes provide a buffering capability and reduce the date I/O overhead. In addition, using the by-passing path provides eight-way connectivity even with four links. with these salient features. SliM shows a significant performance improvement. This paper presents architectures of a PE and the SliM Image Processor, and describes the design of an instruction set.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.17 no.32
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• pp.145-154
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• 1994

In this paper, monitoring processor in a circuit switched network is considered. Monitoring processor monitors communication links, and offers a grade of service in each link to controller. Such an information is useful for an effective maintenance of system. Two links with nonsymmetric system Parameters are considered. each link is assumed independent M/M/1/1 type. The Markov process is introduced to compute busy and idle portions of monitoring processor and monitored rate of each link. Inter-idle times and inter-monitoring times of monitoring processor between two links are respectively computed. A recursive formula is introduced to make computational procedure rigorous.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.5
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• pp.27-36
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• 2004

In this paper, we propose the ethernet Inter-Processor Communication (IPC) network architecture and 10gigabit ethernet frame multiplex/demultiplexer architecture for the edge switch system based on Linux that has 10 Gigabit Ethernet (10Gigabit Ethernet) port with 72Gbps capacities. we discuss the ethernet IPC with ethernet switch and we propose design and implementation of ethernet Inter-Processor Communication (IPC) network architecture and multiple gigabit ethernet frame rnultiplexing/demultiplexing scheme to handle 10gigabit ethernet frame instead of using 10gigabit network processor. And then ethernet Inter-Processor Communication (IPC) network architecture and 10gigabit ethernet frame MUX/DMUX architecture is designed verified and implemented.

• Journal of Korea Multimedia Society
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• v.2 no.4
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• pp.378-389
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• 1999

Parallel tasks in distributed real-time systems can be divided into several subtasks and be executed in parallel according to their real-time attributes. But, it is difficult to gain the optimal solution which is to allocate a tasks deadline into the subtasks deadline while minimizing the subtasks deadline miss. Tn this Paper, we propose the algorithm that allocates deadlines into each subtask, according to the attributes of each subtask(i.e. using communication time and execution time to periodic tasks). Also, we suggest a processor mapping algorithm that considers the communication time among the processors and the effective duplication algorithm which is allocated to the identical processor for the purpose of improving the communication time between the subtasks. We can obtain a result that reduces IPC(Inter-Processor Communication) time and uses the idle processor through applying effective real-time attributes to FUTD(Fully connected, Unbounded Task Duplication) algorithms. As a result, we can improve the average processor utilization.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.255-258
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• 2000

This paper presents an Interprocessor Communication Network(IPC net) in ATM switching system. In order to supply stable and independent path for processor communication, additional network i.e., Ethernet, is suggested. An Ethernet switch centered on Ethernet binds each processor into a work range. IPC net proposed in this paper assures end-to-end inter-processor connection, uniform 100Mbps Ethernet bandwidth and enhanced user cell throughput of ATM switch with minimum Ethernet supporting block integrated into ATM system

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1990.04a
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• pp.326-334
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• 1990

A monitoring process of a communication network with two links is analyzed. The Markov process is introduced to compute busy and idle portions of monitoring processor and monitored rate of each link. Inter-idle times and inter-monitoring ties of monitoring processor between two links are respectively computed. A recursive formula is introduced to make the computational procedure rigorous.

• International Journal of Contents
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• v.1 no.2
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• pp.13-17
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• 2005

Base Station Controller which belongs to IMT-2000(International Mobile Telecommunication - 2000) network has several types of structure for efficient control protocol. This difference of structure occurs two different protocols for call handling. Recently the need of IMT-2000 is highly increasing, so it is important to analyze the performance of processors and IPC(Inter-Processor Communication) module with structure of BSC and protocol difference. This paper presents the performance comparison of different types of BSC in view of processor utilization, waiting time, queue length and QoS(Quality of Service) through the simulation model.