• Title/Summary/Keyword: Inter-Processor Communication

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Inter-GuestOS Communications in Multicore-based ARM TrustZone (멀티코어 프로세서 기반 ARM TrustZone 환경에서의 게스트 운영체제 간 통신)

  • Jeon, Moowoong;Kim, Sewon;Yoo, Hyuck
    • Journal of KIISE
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    • v.42 no.5
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    • pp.551-557
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    • 2015
  • The technology using ARM TrustZone draws attention as a new embedded virtualization approach. The ARM TrustZone defines two virtual execution environment, the secure world and the normal world. In such an environment, the inter-world communication is important to extend function of software. However, the current monitor software does not sufficiently support the inter-world communication. This paper presents a new inter guestOS communication scheme, for each world, for the ARM TrustZone virtualization. The proposed communication scheme supports bidirectional inter-world communication for single core and multicore environment. In this paper, It is implemented on a NVIDIA Tegra3 processor based on the ARM Cortex-A9 MPCore and it showed a bandwidth of 30MB/s.

Structure of Communication Path Between Processors in ATM Switching System and its Test (ATM 교환기에서 제어계간 통신 경로 구성 및 시험)

  • 김영섭;한용민;김철규;전만영;박홍식
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.9
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    • pp.1202-1208
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    • 1995
  • Inter-processor communication is required to manage resources in ATM switching system where processors are distributed. ATM switching system, which was developed in our institute, does't have dedicated communication path for inter-processor communication, but use the ordinary switching network same as user data. Therefore, we should test communication paths and equipments before running various application software programs. In this paper, we propose a method to test communication paths between processors in ATM switching system and describe an implemented program using this method.

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Implementation and Performance Analysis of High Speed Communication Mechanism between Internet Processor and CDMA Processor (인터넷 프로세서와 CDMA 송수신 프로세서간의 고속 데이타 전송 메커니즘 구현 및 성능분석)

  • Jung, Hae-Seung;Chung, Sang-Hwa
    • Journal of KIISE:Computing Practices and Letters
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    • v.8 no.5
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    • pp.590-597
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    • 2002
  • Currently, with the increasing demand for combining cellular phone and PDA, various kinds of PDA-phones are being developed. A typical PDA-phone consists of a CDMA processor and a PDA processor. Generally, a UART serial communication port is used for inter-processor communication. However, the CDMA standard will need more data bandwidth over 2Mbps with the emergence of IMT-2000. The bandwidth requirement is beyond the capability of UART. In this paper, several inter-processor communication mechanisms are analyzed and especially Dual Port Memory and USB were chosen as the candidates for the new communication mechanism. A prototype PDA-phone board has been implemented for experiment. The experimental result shows that Dual Port Memory is better than USB in cost performance.

Design of an Image Processing ASIC Architecture using Parallel Approach with Zero or Little (통신부담을 감소시킨 영상처리를 위한 병렬처리 방식 ASIC구조 설계)

  • 안병덕;정지원;선우명훈
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.10
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    • pp.2043-2052
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    • 1994
  • This paper proposes a new parallel ASIC architecture for real-time image processing to reduce inter-processing element (inter-PE) communication overhead, called a Sliding Memory Plane (SliM) Image Processor. The Slim Image Processor consists of $3\times3$ processing elements (PEs) connected by a mesh topology. With easy scalability due to the topology. a set of SliM Image Processors can form a mesh-connected SIMD parallel architecture. called the SliM Array Processor. The idea of sliding means that all pixels are slided into all neighboring PEs without interrupting PEs and without a coprocessor or a DMA controller. Since the inter-PE communication and computation occur simultaneously. the inter-PE communication overhead, significant disadvantage of existing machines greatly diminishes. Two I/O planes provide a buffering capability and reduce the date I/O overhead. In addition, using the by-passing path provides eight-way connectivity even with four links. with these salient features. SliM shows a significant performance improvement. This paper presents architectures of a PE and the SliM Image Processor, and describes the design of an instruction set.

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Performance Analysis of Monitoring Process using the Stochastic Model (추계적 모형을 이용한 모니터링 과정의 성능 분석)

  • 김제숭
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.17 no.32
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    • pp.145-154
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    • 1994
  • In this paper, monitoring processor in a circuit switched network is considered. Monitoring processor monitors communication links, and offers a grade of service in each link to controller. Such an information is useful for an effective maintenance of system. Two links with nonsymmetric system Parameters are considered. each link is assumed independent M/M/1/1 type. The Markov process is introduced to compute busy and idle portions of monitoring processor and monitored rate of each link. Inter-idle times and inter-monitoring times of monitoring processor between two links are respectively computed. A recursive formula is introduced to make computational procedure rigorous.

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Design and Implementation of 10Gigabit Ethernet System with IPC and Frame MUX/DEMUX Architecture (10기가비트 이더넷 인터페이스를 위한 프레임 다중화기/역다중화기와 IPC를 갖는 10기가비트 이더넷 시스템의 설계 및 구현)

  • 조규인;김유진;정해원;조경록
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.41 no.5
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    • pp.27-36
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    • 2004
  • In this paper, we propose the ethernet Inter-Processor Communication (IPC) network architecture and 10gigabit ethernet frame multiplex/demultiplexer architecture for the edge switch system based on Linux that has 10 Gigabit Ethernet (10Gigabit Ethernet) port with 72Gbps capacities. we discuss the ethernet IPC with ethernet switch and we propose design and implementation of ethernet Inter-Processor Communication (IPC) network architecture and multiple gigabit ethernet frame rnultiplexing/demultiplexing scheme to handle 10gigabit ethernet frame instead of using 10gigabit network processor. And then ethernet Inter-Processor Communication (IPC) network architecture and 10gigabit ethernet frame MUX/DMUX architecture is designed verified and implemented.

Duplication Scheduling of Periodic Tasks Based on Precedence Constraints and Communication Costs in Distributed Real-Time Systems (분산 실시간 시스템에서 우선순위와 통신비용을 고려한 주기적 타스크들의 중복 스케줄링)

  • Park, Mi-Kyoung;Kim, Chang-Soo
    • Journal of Korea Multimedia Society
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    • v.2 no.4
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    • pp.378-389
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    • 1999
  • Parallel tasks in distributed real-time systems can be divided into several subtasks and be executed in parallel according to their real-time attributes. But, it is difficult to gain the optimal solution which is to allocate a tasks deadline into the subtasks deadline while minimizing the subtasks deadline miss. Tn this Paper, we propose the algorithm that allocates deadlines into each subtask, according to the attributes of each subtask(i.e. using communication time and execution time to periodic tasks). Also, we suggest a processor mapping algorithm that considers the communication time among the processors and the effective duplication algorithm which is allocated to the identical processor for the purpose of improving the communication time between the subtasks. We can obtain a result that reduces IPC(Inter-Processor Communication) time and uses the idle processor through applying effective real-time attributes to FUTD(Fully connected, Unbounded Task Duplication) algorithms. As a result, we can improve the average processor utilization.

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Design and Implementation of IPC Network using Ethernet Switch In ATM (ATM 교환기내 Ethernet Switch를 이용한 IPC망 구현)

  • 김법중;나지하;오정훈;안병준
    • Proceedings of the IEEK Conference
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    • 2000.11a
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    • pp.255-258
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    • 2000
  • This paper presents an Interprocessor Communication Network(IPC net) in ATM switching system. In order to supply stable and independent path for processor communication, additional network i.e., Ethernet, is suggested. An Ethernet switch centered on Ethernet binds each processor into a work range. IPC net proposed in this paper assures end-to-end inter-processor connection, uniform 100Mbps Ethernet bandwidth and enhanced user cell throughput of ATM switch with minimum Ethernet supporting block integrated into ATM system

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Performance analysis of monitoring process using the stochastic model (추계적 모형을 이용한 모니터링 과정의 성능 분석)

  • 김제숭;홍정식;이창훈
    • Proceedings of the Korean Operations and Management Science Society Conference
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    • 1990.04a
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    • pp.326-334
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    • 1990
  • A monitoring process of a communication network with two links is analyzed. The Markov process is introduced to compute busy and idle portions of monitoring processor and monitored rate of each link. Inter-idle times and inter-monitoring ties of monitoring processor between two links are respectively computed. A recursive formula is introduced to make the computational procedure rigorous.

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Performance Analysis for Base Station Controller in Mobile Communication Networks

  • Lim Seog-Ku
    • International Journal of Contents
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    • v.1 no.2
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    • pp.13-17
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    • 2005
  • Base Station Controller which belongs to IMT-2000(International Mobile Telecommunication - 2000) network has several types of structure for efficient control protocol. This difference of structure occurs two different protocols for call handling. Recently the need of IMT-2000 is highly increasing, so it is important to analyze the performance of processors and IPC(Inter-Processor Communication) module with structure of BSC and protocol difference. This paper presents the performance comparison of different types of BSC in view of processor utilization, waiting time, queue length and QoS(Quality of Service) through the simulation model.

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