• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.99-104
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• 2013

As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional integration circuit(IC) cannot be a solution for the enhancement of the semiconductor integration circuit technology due to an increase in RC delay among interconnects. To address this problem, a new technology of 3 dimensional integration circuit (3D-IC) has been developing. In this study, three-dimensional integrated device was investigated due to improve of reducing the size, interconnection problem, high system performance and functionality.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.75-80
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• 2004

By the SOG (System-on-Glass) technology with excimer laser anneal process, the number of IC chips and the area of the mounted IC chips on the printed circuit board are reduced. In new circuit integrations on the glass substrate, we have developed D/A converter including the new capacitor array, amplifier comprising the original comparators and new display device with capturing images by integrated sensor into a pixel. This paper discusses the application of circuit integration of low-temperature poly-Si.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.131-137
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• 2016

In this paper, we analyze the impedance analysis of vertical interconnection through-silicon vias (TSV) that is being studied for the purpose of improving the degree of integration and an electric feature in 3D IC. Also, it is to improve the performance and the degree of integration of the three-dimensional integrated circuit system which can exceed the limits of conventional two-dimensional a IC. In the future, TSV technology in full-chip 3-dimensional integrated circuit system design is very important, and a study on the electrical characteristics of the TSV for high-density and high-bandwidth system design is very important. Therefore, we study analyze the impedance influence of the TSV in accordance with the distance and frequency in a multiple TSV-to-TSV for the purpose of designing a full-chip three-dimensional IC. The results of this study also are applicable to semiconductor process tools and designed for the manufacture of a full-chip 3D IC.

• ETRI Journal
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• v.34 no.5
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• pp.706-712
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• 2012

In previous work, novel maskless bumping and no-flow underfill technologies for three-dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low-volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no-flow underfill material named "fluxing underfill" is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two-tier stacked TSV chips are sucessfully stacked.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1666-1671
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• 1989

A novel switched-capacitor circuit for interfacing capacitive microtransducers with a digital system is developed based on the dual-slope integration. It consists of a differential integrator and a comparator. Driven by the teo phase clock, the circuit first senses the capacitance difference between the transducer and the reference capacitor in the form of charge, and accumulates it into the feedback capabitor of the integrator for a fixed period of time. The resulant accumulated charge is next extracted by the known reference charge until the integrator output voltage refurns to zero. The length of time required for the integrator output to return to zero, as measured by the number of clock cycle gated into a counter is proportional to the capacitance difference, averaged over the integration period. The whole operation is insensitive to the reference voltage and the capacitor values involved in the circuit, Thus the proposed circuit permits an accurate differental capacitance measurement. An error analysis has showh that the resolution as high as 8 bits can be expected by realizing the circuit in a monolithic MOS IC form. Besides the accuracy, it features the small device count integrable onto a small chip area. The circuit is thus particularly suitadble for the on-chip interface.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.1
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• pp.35-43
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• 2017

The three-dimensional integrated circuit (3D-IC) is a general trend for the miniaturized and high-performance electronic devices. The through-silicon-via (TSV) is the advanced interconnection method to achieve 3D integration, which uses vertical metal via through silicon substrate. However, the TSV based 3D-IC undergoes severe thermo-mechanical stress due to the CTE (coefficient of thermal expansion) mismatch between via and silicon. The thermo-mechanical stress induces mechanical failure on silicon and silicon-via interface, which reduces the device reliability. In this paper, the thermo-mechanical reliability of TSV based 3D-IC is reviewed in terms of mechanical fracture, heat conduction, and material characteristic. Furthermore, the state of the art via-level and package-level design techniques are introduced to improve the reliability of TSV based 3D-IC.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.431-438
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• 2005

In this paper, we propose the built-in current testing circuit for improving reliability As the integrated CMOS circuits in a chip are increased, the testability on design and fabrication should be considered to reduce the cost of testing and to guarantee the reliability In addition, the high degree of integration makes more failures which are different from conventional static failures and introduced by the short between transistor nodes and the bridging fault. The proposed built-in current testing method is useful for detecting not only these failures but also low current level failures and faster than conventional method. In normal mode, the detecting circuit is turned off to eliminate the degradation of CUT(Circuits Under Testing). The differential input stage in detecting circuit prevents the degradation of CUT in test mode. It is expected that this circuit improves the quality of semiconductor products, the reliability and the testability.

• Journal of Sensor Science and Technology
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• v.3 no.1
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• pp.54-60
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• 1994

In this paper, the multi-sensor signal processing IC is designed. It consists of an analog multiplexer for selection of multi-sensor signals, active filters for noise rejection and signal amplification, and a sample and hold circuit for interface with digital signal processing. By implementing these circuits with CMOS transistors, integration, low power dissipation and miniaturization of the total signal processing system have been made possible.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.861-863
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• 2003

In this work, the preparations and characteristics of capacitors and inductors for RF IC as a integrated devices are investigated. These kinds of capacitors and inductors can be applicable to the passive components utilized in voltage controlled oscillator(VCO), low noise amplifier(LAN), mixer and synthesizer for mobile telecommunication of radio frequency band(900 MHz to 2.2GHz), and in a library of monolithic microwave integrated circuit(MMIC). The results show that these inductors and capacitors array for RF IC may be applicable to the RF IC passive components for mobile telecommunication.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.397-400
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• 1999

As the result of enhancement of CAD, Design Automation and manufacturing technology, it's on the increasing complexity, integration ratio, data signals, and pin count to IC chips. This brings about difficulties of testing, and incresing test time. Now One of the most cost-consuming procedure as integration ratio increases is the testing step. In this paper, we propose a new method, “Efficient TP(test point) assignment algorithm” using “input grouping”, This is helpful method to reducing test length without losing fault coverage. Experimental results show that proposed method reduces test length remarkably and doesn't miss fault coverage, with low hardware overhead Increasing.