• Proceedings of the KIEE Conference
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• 2003.10b
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• pp.137-140
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• 2003

To the optimization design of molded case circuit breakers(MCCBs), it is necessary and important to calculate the electro-dynamic repulsion force acting on the movable conductor. With 3-D finite element nonlinear analysis, according to the equations among current-magnetic field-repulsion force and taking into account the ferromagnet, contact bridge model is introduced to simulate the current constriction between contacts, so Lorentz and Holm force acting on the movable conductor and contact, respectively, can be integrated to calculate. Coupled with circuit equations, the opening time of movable contact also can be obtained using iteration with the restriction of contact force. Simulation and experiment for repulsion forte and opening time of five different configuration models have been investigated. The results indicate that the proposed method is effective and capable of evaluating new design of contact systems in MCCBs.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.33 no.10
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• pp.1163-1170
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• 2009

Reliability analysis is of great importance in the advanced product design, which is to evaluate reliability due to the associated uncertainties. There are three types of uncertainties: the first is the aleatory uncertainty which is related with inherent physical randomness that is completely described by a suitable probability model. The second is the epistemic uncertainty, which results from the lack of knowledge due to the insufficient data. These two uncertainties are encountered in the input variables such as dimensional tolerances, material properties and loading conditions. The third is the metamodel uncertainty which arises from the approximation of the response function. In this study, an integrated method for the reliability analysis is proposed that can address all these uncertainties in a single Bayesian framework. Markov Chain Monte Carlo (MCMC) method is employed to facilitate the simulation of the posterior distribution. Mathematical and engineering examples are used to demonstrate the proposed method.

• The Bulletin of The Korean Astronomical Society
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• v.42 no.2
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• pp.88.1-88.1
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• 2017

We report a novel design of the "linear astigmatism-free" three mirror system (LAF-TMS). In general, the linear astigmatism is one of the most dominant aberration degrading image qualities in common off-axis systems. The proposed LAF-TMS is based on a confocal off-axis three mirror system, where higher order aberrations are minimized via our numerical optimization. The system comprises three pieces of aluminum-alloy freeform mirrors that are feasible to be fabricated with current single-point diamond turning (SPDT) machining technology. The surface figures, dimensions, and positions of mirrors are carefully optimized for a LAF performance. For higher precision-positioning mechanism, we also included alignment parts: shims (for tilting) and L-brackets (for decentering). Any possible mechanical deformation due to assembly process as well as 1-G gravity, and its influence on optical performances of the system are investigated via the finite element (FE) analysis. The LAF-TMS has low f-number and a wide field of view, which is promising for sky monitoring programs such as supernova surveys.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.443-450
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• 2014

This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

• International Journal of Naval Architecture and Ocean Engineering
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• v.10 no.1
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• pp.37-47
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• 2018

Dynamic simulation is critical for electrical ship studies as it obtains the necessary information to capture and characterize system performance over the range of system operations and dynamic events such as disturbances or contingencies. However, modeling and simulation of the interactive electrical and mechanical dynamics involves setting up and solving system equations in time-domain that is typically time consuming and computationally expensive. Accurate assessment of system dynamic behaviors of interest without excessive computational overhead has become a serious concern and challenge for practical application of electrical ship design, analysis, optimization and control. This paper aims to develop a systematic approach to classify the sophisticated dynamic phenomenon encountered in electrical ship modeling and simulation practices based on the design intention and the time scale of interest. Then a novel, comprehensive, coherent, and end-to-end mathematical modeling and simulation approach has been developed for the latest Medium Voltage Direct Current (MVDC) Shipboard Power System (SPS) with the objective to effectively and efficiently capture the system behavior for ship-wide system-level studies. The accuracy and computation efficiency of the proposed approach has been evaluated and validated within the time frame of interest in the cast studies. The significance and the potential application of the proposed modeling and simulation approach are also discussed.

• Structural Engineering and Mechanics
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• v.76 no.4
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• pp.451-463
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• 2020

In this paper, a new semi-analytical solution for estimating the pull-in parameters of electrically actuated functionally graded (FG) nanobeams is proposed. All the bulk and surface material properties of the FG nanoactuator vary continuously in thickness direction according to power law distribution. Here, the modified couple stress theory (MCST) and Gurtin-Murdoch surface elasticity theory (SET) are jointly employed to capture the size effects of the nanoscale beam in the context of Euler-Bernoulli beam theory. According to the MCST and SET and accounting for the mid-plane stretching, axial residual stress, electrostatic actuation, fringing field, and dispersion (Casimir or/and van der Waals) forces, the nonlinear nonclassical equation of motion and boundary conditions are obtained derived using Hamilton principle. The proposed semi-analytical solution is derived by employing Galerkin method in conjunction with the Particle Swarm Optimization (PSO) method. The proposed solution approach is validated with the available literature. The freestanding behavior of nanoactuators is also investigated. A parametric study is conducted to illustrate the effects of different material and geometrical parameters on the pull-in response of cantilever and doubly-clamped FG nanoactuators. This model and proposed solution are helpful especially in mechanical design of micro/nanoactuators made of FGMs.

• Journal of Information Processing Systems
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• v.15 no.2
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• pp.374-385
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• 2019

This paper presents an optimal implementation of a Daubechies-based pipelined discrete wavelet packet transform (DWPT) processor using finite impulse response (FIR) filter banks. The feed-forward pipelined (FFP) architecture is exploited for implementation of the DWPT on the field-programmable gate array (FPGA). The proposed DWPT is based on an efficient transpose form structure, thereby reducing its computational complexity by half of the system. Moreover, the efficiency of the design is further improved by using a canonical-signed digit-based binary expression (CSDBE) and advanced functional sharing (AFS) methods. In this work, the AFS technique is proposed to optimize the convolution of FIR filter banks for DWPT decomposition, which reduces the hardware resource utilization by not requiring any embedded digital signal processing (DSP) blocks. The proposed AFS and CSDBE-based DWPT system is embedded on the Virtex-7 FPGA board for testing. The proposed design is implemented as an intellectual property (IP) logic core that can easily be integrated into DSP systems for sub-band analysis. The achieved results conclude that the proposed method is very efficient in improving hardware resource utilization while maintaining accuracy of the result of DWPT.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.43-51
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• 2014

In 3-dimensional (3D) integrated package, thermal management is one of the critical issues due to the high heat flux generated by stacked multi-functional chips in miniature packages. In this study, we used numerical simulation method to analyze the thermal behaviors, and investigated the thermal issues of 3D package using TSV (through-silicon-via) technology for mobile application. The 3D integrated package consists of up to 8 TSV memory chips and one logic chip with a interposer which has regularly embedded TSVs. Thermal performances and characteristics of glass and silicon interposers were compared. Thermal characteristics of logic and memory chips are also investigated. The effects of numbers of the stacked chip, size of the interposer and TSV via on the thermal behavior of 3D package were investigated. Numerical analysis of the junction temperature, thermal resistance, and heat flux for 3D TSV package was performed under normal operating and high performance operation conditions, respectively. Based on the simulation results, we proposed an effective integration scheme of the memory and logic chips to minimize the temperature rise of the package. The results will be useful of design optimization and provide a thermal design guideline for reliable and high performance 3D TSV package.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.36 no.4
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• pp.361-371
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• 2012

In order to improve the efficiency of the branch-and-bound method for mixed-discrete nonlinear programming, a nonuniform convergence tolerance scheme is proposed for the continuous subproblem optimizations. The suggested scheme assigns the convergence tolerances for each continuous subproblem optimization according to the maximum constraint violation obtained from the first iteration of each subproblem optimization in order to reduce the total number of function evaluations needed to reach the discrete optimal solution. The proposed tolerance scheme is integrated with five branching order options. The comparative performance test results using the ten combinations of the five branching orders and two convergence tolerance schemes show that the suggested non-uniform convergence tolerance scheme is obviously superior to the uniform one. The results also show that the branching order option using the minimum clearance difference method performed best among the five branching order options. Therefore, we recommend using the "minimum clearance difference method" for branching and the "non-uniform convergence tolerance scheme" for solving discrete optimization problems.