• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1213-1215
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• 2007

The OTFT technologies have been mature almost up to the level of commercialization. In this paper we report the OTFT's applications to the backplane for active matrix electrophoretic, active matrix OLED and to integrated circuits. In addition we also introduce the recently developed technologies for reduction of OTFT's operating voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.728-732
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• 2014

Macro-model of magnetic tunnel junction (MTJ) for spin transfer torque magnetic random access memory (STT-MRAM) has been developed. The macro-model can describe the dynamic behavior such as the state change of MTJ as a function of the pulse width of driving current and voltage. The statistical behavior has been included in the model to represent the variation of the MTJ characteristic due to process variation. The macro-model has been developed in Verilog-A.

• 전자공학회논문지A
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• 제30A권6호
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• pp.58-65
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• 1993

In this research, we developed a new algorithm for hierarchical placement of integrated circuits. For efficient placement of a large circuit, the given circuit is recursively partitioned to form a hierarchy tree and then simulated-annealing-based placement method is applied at each level of the hierarchy to find a near optimum solution. During the placemtnt, global optimization is performed at high levels of the hierarchy and local optimization is performed at low levels. When compared with conventional placement methods, the new hierarchical placement method produced favorable results.

• 컴퓨터교육학회논문지
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• 제10권5호
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• pp.53-60
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• 2007

학습효율의 향상을 위해 본 논문에서는 웹기반 가상실험시스템과 원격실험시스템을 적절하게 통합하여 전기전자회로에 대한 하이브리드 실험시스템을 구현하였다. 먼저, 전기/전자회로 실험에 대한 웹기반 가상실험실을 개발하여 개념학습, 가상실험, 평가등의 3개의 주요 세션과 그에 대한 관리시스템으로 구성하였다. 다음으로 가상실험을 진행하는 동안 발생할 수 있는 현실감의 부족성 문제를 해결하기 위해 전기전자회로에 대한 원격실험시스템을 구현하였다. 제안된 가상/원격실험시스템은 독립적인 형태로 사용될 수도 있지만, 학습효율을 극대화하기 위해서 두 개의 시스템을 통합하여 하이브리드 전기전자 실험시스템을 구현하였다.

• 대한전자공학회논문지
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• 제25권5호
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• pp.509-521
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• 1988

In the designs of integrated circuits, the buffer circuits used for driving a large capacitive load from minimum-structured logic circuit outputs have important effects upon system throughputs. Therefore it is important to optimize the buffer circuits. In this paper, the principle of designing CMOS buffer circuits which have the minimum delay and drive the given capacitive load is discussed. That is, the effects of load capacitance upon rise time, fall time, and delay of the CMOS inverter and the effects of parasitic capacitances are finely analysed to calculate the requested minimum-delay CMOS buffer condition. This is different from the method by C.A. Mead et. al.[2.3.4.]which deals with passive-load-nMOS buffers. Large channel width MOS transistor stages are necessary to drive a large capacitive load. The effects of polysilicon gate resistances of such large stages upon delay are also analysed.And, the area of buffer circuits designed by the proposed method is smaller than that of buffer circuits designed by C.A. Mead's method.

• 한국결정성장학회지
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• 제13권1호
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• pp.15-18
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• 2003

High purity single crystalline calcium fluoride ($CaF_2$) has excellent optical transmission characteristics down to deep UV and is therefore selected as the main optical material for the next generation of lithography apparatus operating at wavelength of 157 nm. The growth of large sized $CaF_2$ single crystals with the required properties for this optical application can be achieved only by optimizing the crystal growth process by the aid of numerical simulation. This needs especially a precise calculation of the heat transport and temperature distribution in the solid and liquid $CaF_2$ under crystal growth conditions. As $CaF_2$ is considered to be semitransparent, the internal radiative heat transfer in $CaF_2$ plays an decisive role in the simulation of the heat transport. On the other hand it is very difficult to obtain quantitative experimental data for evaluating numerical models as $CaF_2$ is extremely corrosive at high temperatures. In this work we present a newly developed experimental technique to perform temperature measurements in $CaF_2$-crystal as well as in the melt under conditions of crystal growth process. These experimental results are compared to calculated temperature data, which were obtained by using different numerical models concerning the internal heat transfer in semitransparent $CaF_2$. It will be shown, that an advanced model, which was developed by the authors, gives a much better agreement with experimental data as a standard model, which was taken from the literature.

• KIEE International Transactions on Electrophysics and Applications
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• 제4C권6호
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• pp.255-262
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• 2004

In this paper, a number of double-layered microwave integrated circuits (MIC) have been designed and analyzed based on a developed finite-difference time-domain (FDTD) solver. The solver was first validated through comparisons of the computed results with those previously published throughout the literature. Subsequently, various double-layered MIC printed on both isotropic and anisotropic substrates and superstrates, which are frequently encountered in printed circuit boards (PCB), have been designed and analyzed. It was found that in addition to protecting circuits, the added superstrate layer can increase freedoms of design and improve circuit performance, and that the FDTD is indeed a robust and versatile tool for multilayer circuit design.

• ETRI Journal
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• 제33권5호
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• pp.818-821
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• 2011

A D-band subharmonically-pumped resistive mixer has been designed, processed, and experimentally tested. The circuit is based on a $180^{\circ}$ power divider structure consisting of a Lange coupler followed by a ${\lambda}$/4 transmission line (at local oscillator (LO) frequency). This monolithic microwave integrated circuit (MMIC) has been realized in coplanar waveguide technology by using an InAlAs/InGaAs-based metamorphic high electron mobility transistor process with 100-nm gate length. The MMIC achieves a measured conversion loss between 12.5 dB and 16 dB in the radio frequency bandwidth from 120 GHz to 150 GHz with 4-dBm LO drive and an intermediate frequency of 100 MHz. The input 1-dB compression point and IIP3 were simulated to be 2 dBm and 13 dBm, respectively.

• International journal of advanced smart convergence
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• 제12권4호
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• pp.1-7
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• 2023

Large-size, organic light-emitting device (OLED) panels based on highly reliable gate driver circuits integrated using InGaZnO thin film transistors (TFTs) were developed to achieve ultra-high resolution TVs. These large-size OLED panels were driven by using a novel gate driver circuit not only for displaying images but also for sensing TFT characteristics for external compensation. Regardless of the negative threshold voltage of the TFTs, the proposed gate driver circuit in OLED panels functioned precisely, resulting from a decrease in the leakage current. The falling time of the circuit is approximately 0.9 ㎲, which is fast enough to drive 8K resolution OLED displays at 120 Hz. 120 Hz is most commonly used as the operating voltage because images consisting of 120 frames per second can be quickly shown on the display panel without any image sticking. The reliability tests showed that the lifetime of the proposed integrated gate driver is at least 100,000 h.

• ETRI Journal
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• 제36권6호
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• pp.931-941
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• 2014

Many methodologies for clock mesh networks have been introduced for two-dimensional integrated circuit clock distribution networks, such as methods to reduce the total wirelength for power consumption and to reduce the clock skew variation through consideration of buffer placement and sizing. In this paper, we present a methodology for clock mesh to reduce both the clock skew and the total wirelength in three-dimensional integrated circuits. To reduce the total wirelength, we construct a smaller mesh size on a die where the clock source is not directly connected. We also insert through-silicon vias (TSVs) to distribute the clock signal using an effective clock TSV insertion algorithm, which can reduce the total wirelength on each die. The results of our proposed methods show that the total wirelength was reduced by 12.2%, the clock skew by 16.11%, and the clock skew variation by 11.74%, on average. These advantages are possible through increasing the buffer area by 2.49% on the benchmark circuits.