• Journal of the Korean Society for Library and Information Science
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• v.58 no.1
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• pp.31-51
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• 2024

The purpose of this study is to propose a design model for school library based instruction under EduTech. EduTech-based education expands learning boundaries and requires new instructional environments and learning experiences for learner-centered deeper learning. Accordingly, this study modified the ADDIE model based on the system theory and presented a four-stage instructional design model (draft) consisting of 'analysis stage, preliminary learning and development stage, learning management stage, and team teaching evaluation stage.' This model reflects elements of flipped learning, the backward design model, and inquiry-based learning to develop of customized student materials and inquiry activities. In addition, the scope of learning was expanded to include prior learning, face-to-face learning, and additional learning to increase the diversity of collaboration and opportunities to utilize school library materials. Also, Several ways for school library based instruction within EduTec were proposed in terms of teacher librarians' expertise, school library space, budget, standard curriculum development, and comprehensive support system for reading education.

• Journal of Korean Home Economics Education Association
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• v.23 no.1
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• pp.113-141
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• 2011

The purpose of this study was to examine the effects of home economics instruction in food labeling using a motivational(ARCS-Attention, Relevance, Confidence, and Satisfaction) strategy to increase middle school students' learning motivation, recognition and use of food labels. To achieve this purpose, teaching-learning plans of food label instruction using a motivation(ARCS) strategy were developed over four class periods using a pretest-posttest experimental design. The experiment was conducted across two groups as follows: 4 experimental groups that received the motivation(ARCS) strategy instruction, and 3 comparative groups that received lecture type instruction. The pretest-posttest scores of the experimental and comparative groups were compared. The 203 data of questionnaires for the experiment were analyzed and evaluated by Analysis of Covariance(ANCOVA) using SPSS Win 12,0. The results of this study were as follows: First, teaching-learning plans, learning materials, and teacher reference materials for the home economics food label instruction that applied the motivation(ARCS) strategy were developed in five subject areas: nutrition labels, food additives, genetically modified food, irradiated food, and food quality verification labels. Second, students' learning motivation of the two groups showed statistically meaningful differences. Home economics instruction using a motivation(ARCS) strategy was more effective in increasing students' learning motivation than lecture type instruction. Third, as a result of ANCOVA which regulated the recognition of food labels in the pre-experimental design, the recognition of food labels in the post-experimental design showed the meaningful differences depending on the instruction style(motivation strategy and lecture type instruction). In addition, comprehensibility, practical use and educational necessity of food label details showed statistically meaningful differences. Home economics instruction using motivation(ARCS) strategy was more effective than lecture type instruction in improving students' recognition of food labeling. Fourth, as a result of ANCOVA which regulated the use of food labels in the pre-experimental stage, the use of food labels in the post-experimental stage showed meaningful differences between experimental and comparative groups depending on the instruction style. Therefore, home economics instruction in food labeling using motivation(ARCS) strategy was more effective than lecture type instruction in increasing students' use of food labels.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.39 no.8
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• pp.875-887
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• 1990

It is hard to keep good quality of coursewares for Computer-Assisted Instruction (CAI), since most CAI coursewares have been developed by programmers rather than by instruction designers. Also, there is no trasplantations among authoring system. This paper describes the design and implementation of an authoring system for CAI to overcome the problems mentioned above. The performance of the system is assured experimentally and then good results are shown compared with other systems.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.200-203
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• 2000

In this paper, we describes the design of a CPU compatible with ARM9 processor. The CPU is fully synthesizable and described in Verilog-XL. Starting from the synthesizable ARM7 compatible CPU we developed earlier, we modified its pipeline to five stages. For this we first partition the behaviors of each instruction into five stage pipeline operations. Then we designed the controller and the datapath considering the forwarding or interlock schemes. Finally the compatibility of the designed CPU is verified by comparing the results of every instruction executed in test programs with those of the reference simulator developed for the ARM7 compatible CPU.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.357-360
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• 2001

As SOC design methodology becomes popular, processors, the essential core in embedded system are required to be designed fast and supported to customers with expansive behavior description. This paper presents new methodology to meet such goals with designer configurable instruction set simulator for processors. This paper proposes new language called PML(Processor Modeling Language), which is based on microprogramming scheme and is also successful in most behavior of processors. By using this, we can describe scalar processor very efficiently with by-far faster simulation speed in compared with HDL model.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.56-62
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• 2008

Modern microprocessors must deliver high application performance, while the design process should not subordinate power. In terms of performance and power tradeoff, the instructions window is particularly important. This is because a large instruction window leads to achieve high performance. However, naive scaling conventional instruction window can severely affect the complexity and power consumption. This paper explores an architecture level approach to reduce power dissipation. We propose a low power issue logic with an efficient tag translation. The direct lookup table (DTL) issue logic eliminates the associative wake-up of conventional instruction window. The tag translation scheme deals with data dependencies and resource conflicts by using bit-vector based structure. Experimental results show that, for SPEC2000 benchmarks, the proposed design reduces power consumption by 24.45% on average over conventional approach.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.241-251
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• 2007

Energy consumption in the instruction cacheaccounts for a significant portion of the total processor energy consumption. Therefore, reducing energy consumption in the instruction cache is important in designing embedded processors. This paper proposes a method for reducing dynamic energy consumption in the instruction cache by partitioning it to smaller (less energy-consuming) sub-caches. When a request comes into the proposed cache, only one sub-cache is accessed by utilizing the locality of applications. By contrast, the other sub-caches are not accessed, leading todynamic energy reduction. In addition, the proposed cache reduces dynamic energy consumption by eliminating the energy consumed in tag matching. We evaluated the energy efficiency by running cycle accurate simulator, SimpleScalar. with power parameters obtained from CACTI. Simulation results show that the proposed cache reduces dynamic energy consumption by $37%{\sim}60%$ compared to the traditional direct-mapped instruction cache.

• Journal of The Korean Association of Information Education
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• v.7 no.3
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• pp.263-274
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• 2003

Web based instruction (WBI) has been widely used thesedays because the web has various advantages for instruction. However, most of current WBI systems do not support various requirements from students. It is because of the lack of research for structural instruction method. This paper presents a new method of WBI and designs an instruction model to support various requirements from students by implementing dynamic WBI system using JSP to solve current WBI problems. The developed WBI system uses multimedia based instructions. The implemented system focused on the practical instruction by providing the functions of listening, homework, and test on web site. For the similar effects as in the classroom, it supports functions of electronic white board and multimedia data which is consisted of high-quality sound and video data with high degree of compression. Furthermore, the system supports that instructors can design a test using three kinds of basic forms, a multiple-choice test, brief-answer test, essay test, and evaluate the tests easily. It also supports easy management for homework, lecture registration, and many school affairs.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.8
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• pp.741-751
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• 2000

To achieve high performance by exploiting instruction level parallelism aggressively in superscalar processors, it is necessary to overcome the limitation imposed by control dependences and data dependences which prevent instructions from executing parallel. Value prediction is a technique that breaks data dependences by predicting the outcome of an instruction and executes speculatively its data dependent instruction based on the predicted outcome. In this paper, a hybrid value prediction scheme with dynamic classification mechanism is proposed. We design a hybrid predictor by combining the last predictor, a stride predictor and a two-level predictor. The choice of a predictor for each instruction is determined by a dynamic classification mechanism. This makes each predictor utilized more efficiently than the hybrid predictor without dynamic classification mechanism. To show performance improvements of our scheme, we simulate the SPECint95 benchmark set by using execution-driven simulator. The results show that our scheme effect reduce of 45% hardware cost and 16% prediction accuracy improvements comparing with the conventional hybrid prediction scheme and two-level value prediction scheme.

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.165-167
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• 2006

In this paper we present a new-generation sensor network processor which is not optimized in circuit level, but in system architecture level. The new design build on a conventional processor architecture, improving the design by focusing on application oriented specification, ISA, and micro-architectural optimization that reduce overall design size and advance energy-per-instruction. The design employs harvard architecture, 8-bit data paths, and an compact 19 bit wide RISC ISA. The design also features a unique interrupt handler which offloads periodical monitoring jobs from the main part of CPU. Our most efficient design is capable of running at 300 KHz (0.3 MIPS) while consuming only about few pJ/instruction.