1 |
D. Ernst. Cyclone: A Low-Complexity Broadcast-Free Dynamic Instruction Scheduler, In Proceedings of the IEEE International Symposium on Computer Architecture, 2003
|
2 |
SPEC CPU2000, http://www.spec.org/cpu/
|
3 |
S. Weiss, J. Smith, Instruction Issue Logic in Pipelined Supercomputers, IEEE Transactions on Computers, vol.39, no.3, 1990
|
4 |
D. Ponomarev, G. Kucuk, and K. Ghose, Reducing Power Requirements of Instruction Scheduling Through Dynamic Allocation of Multiple Datapath Resources, In the Proceedings of International Symposium on Microarchitecture, Dec. 2001
|
5 |
A. Buyuktosunoglu, D. Albonesi, S. Schuster, D. Brooks, P. Bose and P. Cook. A Circuit Level Implementation of an Adaptive Issue Queue for Power-Aware Microprocessors, In the Proceedings of the GLSVLSI, 2001
|
6 |
R. Canal. Reducing The Complexity of The Issue Logic, In Proceedings of the ACM International Conference of Supercomputing, 2001
|
7 |
T. Ehrhart. Reducing the Scheduling Critical Cycle using Wakeup Prediction, In the Proceedings of the International Symposium on High-Performance Computer Architecture, 2004
|
8 |
Sim-Panalyzer, v2.0.2, http://www.eecs.umich.edu/ panalyzer/
|
9 |
Y. Weinraub. Power-Aware Out-of-Order Issue Logic in High-Performance Microprocessors, Microprocessors and Microsystems, 30(7): 457-467, 2006
DOI
ScienceOn
|