• Journal of the Institute of Electronics Engineers of Korea SD
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• 제43권2호
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• pp.51-59
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• 2006

Von Neumann architecture suffers from the interface between the central processing unit and the memory, which is called 'Von Neumann bottleneck' In this paper, we propose a scalable general-purpose associative processor (AP) based on content-addressable memory (CAM) which solves this problem and is suitable for the search-oriented applications. We propose an efficient instruction set and a structural scalability to extend for larger applications. We define twelve instructions and provide some reduced instructions to speed up which execute two instructions in a single instruction cycle. The proposed AP performs in a bit-serial, word-parallel fashion and can be considered as a 32-bit general-purpose parallel processor with a massively parallel SIMD structure. We design and simulate a maximum/minumum search greater-than/less-than search, and parallel addition to verify the proposed architecture. The algorithms are executed in a constant time O(k) regardless of the number of input data.

• Journal of Korea Multimedia Society
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• 제14권3호
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• pp.462-470
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• 2011

Retargetability is typically achieved by providing target machine information, ADL, as input. The ADL are used to specify processor and memory architectures and generate software toolkit including compiler, simulator, etc. Simulator are critical components of the exploration and software design toolkit for the system designer. They can be used to perform diverse tasks such as verifying the functionality and/or timing behavior of the system, and generating quantitative measurements(e.g., power energy consumption) which can be used to aid the design process. In this paper, we generate the energy consumption estimation simulator through ADL. For this goal, firstly, we describes the energy consumption estimation and monitoring informations on the ADL based on EXPRESSION. Secondly, we generate the energy estimation and monitoring simulation library and then constructs the simulator, RenergySim. Lastly, we represent the energy estimations results for MIPS R4000 ADL description. From this subjects, we contribute to the efficient architecture developments and prompt SDK generation through programmable experiments in the field of mobile software development.

• ETRI Journal
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• 제25권5호
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• pp.337-344
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• 2003

In this paper, we introduce a fully synthesizable 32-bit embedded microprocessor core called the AE32000B. The AE32000B core is based on the extendable instruction set computer architecture, so it has high code density and a low memory access rate. In order to improve the performance of the core, we developed and adopted various design options, including the load extension register instruction (LERI) folding unit, a high performance multiply and accumulate (MAC) unit, various DSP units, and an efficient coprocessor interface. The instructions per cycle count of the Dhrystone 2.1 benchmark for the designed core is about 0.86. We verified the synthesizability and the area and time performances of our design using two CMOS standard cell libraries: a 0.35-${\mu}m$ library and a 0.18-${\mu}m$ library. With the 0.35-${\mu}m$ library, the core can be synthesized with about 47,000 gates and operate at 70 MHz or higher, while it can be synthesized with about 53,000 gates and operate at 120 MHz or higher with the 0.18-${\mu}m$ library.

• Journal of the Korean Society of Costume
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• 제57권3호
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• pp.136-149
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• 2007

This study researched the costume manufacture process by having the musical 'Christmas Carol' as an example and specifically presented the costume manufacture process of an actually performance work, thus it aimed to be helpful theoretically and realistically, by allowing theatrical costume manufacturers and majors in theatrical costume to be informed of the systematically practical affair process of the theatrical costume manufacture and by exhibiting the research work of costume composition aiming at reproducing a silhouette in the process such as costume composition and sewing, and the effectively manufacturing methods such as the costume composition application and the sewing method development aiming at the activity of performers. In the empirical research, it analyzed the features of characters and arranged the manufacture points while actually manufacturing the performance costume, and clarified the systematically performance costume manufacture process such as a manufacture meeting${\rightarrow}$costume list preparation$\rightarrow$work-instruction sheet preparation$\rightarrow$pattern manufacture$\rightarrow$sewing$\rightarrow$performance and inspection. Through performing the manufacture of the really performance work, it is hoped that this study contributes to the development of performance art circles, by presenting a step and a method of professionally theatrical costume to the performance manufacturers and the theatrical costume manufacturers at present when the theatrical costume is solidifying its position as a professional sphere, in the performance and an, has a meaning as the initially empirical research, which can exhibit as a guide of realistically and empirically educational contents for theatrical costume aiming to bring up professional staff for theatrical costume, and becomes help in the efficiently theatrical costume manufacture realistically.

• Journal of the Korean Institute of Telematics and Electronics C
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• 제36C권4호
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• pp.31-43
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• 1999

The main goal of this paper is to design a high performance SVP(Stack based Video Processor) for network applications. The SVP is a comprehensive scheme; 'better' in the sense that it is an optimal selection of previously proposed enhancements of a stack machine and a video processor. This can process effectively object-based video data using a S-RISC(Stack-based Reduced Instruction Set Computer) with a semi -general-purpose architecture having a stack buffer for OOP(Object-Oriented Programming) with many small procedures at running programs. And it includes a vector processor that can improve the MPEG coding speed. The vector processor in the SVP can execute advanced mode motion compensation, motion prediction by half pixel and SA-DCT(Shape Adaptive-Discrete Cosine Transform) of MPEG-4. Absolutors and halfers in the vector processor make this architecture extensive to a encoder. We also designed a VLSI stack-oriented video processor using the proposed architecture of stack-oriented video decoding. It was designed with O.5$\mu\textrm{m}$ 3LM standard-cell technology, and has 110K logic gates and 12 Kbits SRAM internal buffer. The operating frequency is 50MHz. This executes algorithms of video decoding for QCIF 15fps(frame per second), maximum rate of VLBV(Very Low Bitrate Video) in MPEG-4.

• Journal of The Korean Association For Science Education
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• 제13권3호
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• pp.366-376
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• 1993

In this study, a part of high school science instructional materials is evaluated by Instructional Quality Profile(IQP) based on the Merrill's Component Display Theory(CDT). The CDT is based on the Gagne's assumption of different conditions of learning for different outcomes. The IQP enables the user to check both the consistency and adequacy of existing cognitive instruction. The IQP can be used to predict student performance, and also to design and develop new instructional materials. The instructional components are classified according to 5 task levels; An Use-Generalities on Newly Encountered Examples(UGeg), A Remember-Paraphrased-Generalities(RpG), A Remember-Verbatim-Generalities(RvG), A Remember-Paraphrased-Examples (Rpeg). A Remember-Verbatim-Examples (Rveg). The analyses are composed of 3 parts; Justifying the task level of objectives, Objective-test consistency, and Test-presentation consistency. The objectives, the presentations and the tests given in a teacher's guide and a textbook are analyzed. The results show that the task levels and the content levels of the objectives are not consistent with those of the tests. And the indices of the test-presentation consistency indicate the presentation problems of the instructional materials.

• Journal of The Korean Association of Information Education
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• 제8권1호
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• pp.125-137
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• 2004

This research presents a performance assessment system of which the purpose is to increase the effectiveness of the instruction and learning through the on-the-job superintendent of the instructor, the self-directed learning of the learner, and the interaction between instructors and students. The presented performance assessment system applies the problem-based situated learning of the web-based performance assessment to the production, the execution, the assessment, and the transmission of the test. For the effective administration and learning in the school, we applies the Problem-Based Learning of constructivism and the web-based situated learning of the learning community to the system design. The production of the web-based performance assessment shows that the problem-based and self-directed learning of the assessment are achieved through the web-based automatic production of the performance assessment, and the contextual learning by case-based learning is performed by the production of the template of the performance assessment.

• Journal of Engineering Education Research
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• 제5권1호
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• pp.50-58
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• 2002

The most important point in electronic learning(e-learning) is to gain the learning sympathy by improving interaction among the learners, instructors and operators around instruction contents. But it is necessary for the instructor to have active assistance of an administrator as a supporter and an operator because instructors do not accept all the learner's demands. So, operator's activity is very critical in success of e-learning. In this paper, wamine the theory of constructionism to effectively reflect the characteristic of WWW, and to build up a foundation of the web-based integrated e-learning circumstance. The circumstance is composed of 3 modules of the learner, instructor and the administrator. This aims to coordinate instruction functions in order to improve the effect of learning and to intensify the interaction. This paper presents the design and implementation of an e-learning system which is focused on the administrator's module to effectively support the operator's activity. As a result of this research, the system can be used in building up a variety of e-learning in university, that is, general training course and technical training course.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제48권12호
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• pp.58-65
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and variable point 2D SAD hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the SAD unit and its parallel operations using pattern information, the proposed IME instructions support not only full search algorithms but also other fast search algorithms. The hardware size is 25.5K gates for each Processing Element Group (PEG) which has 128 SAD Processor Elements (PEs). The proposed ASIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The hardware size is 453K gates for the IME unit and the operating frequency is 188MHz for 1080p@30 frame in real time. The proposed ASIP can reduce the hardware size about 26% and the number of operation cycles about 18%.

• The KIPS Transactions:PartB
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• 제8B권6호
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• pp.595-600
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• 2001

Recently, WBI model which is based on web has been proposed in the part of the new activity model of teaching-learning. The demand for the customized coursewares which is required from the learners is increased, the needs of the efficient and automated education agents in the web-based instruction are recognized. But many education systems that had been studied recently did not service fluently the courses which learners had been wanting and could not provide the way for the learners to study the learning weakness which is observed in the continuous feedback of the course. In this paper we propose design of multi-agent system for course scheduling of learner-oriented using weakness analysis algorithm. First, proposed system monitors learner's behaviors constantly, evaluates them, and calculates his accomplishment. From this accomplishment, the multi-agent schedules the suitable course for the learner. The learner achieves an active and complete learning from the repeated and suitable course.