• 한국비블리아학회지
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• 제21권2호
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• pp.111-127
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• 2010

본 연구의 목적은 도서관 활용수업에서 사서교사와 교과교사의 협동수업을 향상하기 위한 교수설계전략을 개발하는 것이다. 협동수업은 학교 공동체에서 사서교사의 교수자로서의 역할을 강화할 수 있는 중요한 경영 활동이다. 그러나 협동수업의 실천 전략인 도서관 활용수업은 협력수준에서 이루어지고 있으며 자료 선정을 제외하고는 교과교사가 교수-학습활동을 주도하고 있는 실정이다. 도서관 활용수업은 자원기반학습이기 때문에 정보활용교육의 방법적 지식과 교과의 학습주제가 통합되도록 설계되어야 한다. 그리고 수업 준비 과정에서 나타날 수 있는 시행착오를 줄이고 성공을 확산시킬 수 있어야 한다. 이러한 측면에서 도서관 활용수업용 협동수업 설계 전략을 '협동수업 상황기술-공동설계-공동수업-공동평가'와 같이 설정하였다

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.105-108
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• 2001

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.

• 정보와 통신
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• 제25권12호
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• pp.10-18
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• 2008

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

• 한국도서관정보학회지
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• 제28권
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• pp.93-135
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• 1998

The purpose of this study was to compare the effectiveness of programmed instruction versus lecture and discussion method on the knowledge of basic reference sources among undergraduate library and information science students. The hypotheses of the study were: 1. Programmed instruction will be more effective than the lecture/discussion method with regard to academic achievement. 2. There will be a significant difference in learning time between the experimental and the control groups. Seventy-eight library and information science students were participated m the study from the two universities in Chungchong Province. A programmed instruction manual, including 4-types of reference sources-dictionary, encyclopaedia, bibliography, indexes and abstracts, 40-item multiple choice post-test, and a questionnaire for the students' attitude toward programmed instruction were developed specifically for this research. The post-test only control-group design was selected for this experimental study. Students were given instruction on the specific reference titles in dictionary, encyclopedia, bibliography, indexes and abstracts. The control group was instructed by the lecture and discussion method while the experimental group completed a programmed instruction manual by themselves. Both the control and the experimental group were tested right after the instruction of 4-types of reference sources. In addition, a questionnaire asking students' attitude toward programmed instruction was administered to the experimental group. The findings from this study are summarized as follows: 1. The results showed that there were no significant difference in the mean of the post test score between the two groups. Therefore, programmed instruction is viable as an alternative method of instruction in the teaching of reference sources. 2. There was a significant difference in the mean of time spending for the leaning of bibliography, indexes and abstracts between the two groups. Accordingly, programmed instruction proved to be more efficient than the conventional lecture/discussion method in terms of learning time. 3. Students showed positive response to programmed instruction and evaluated it very interesting and challenging. In conclusion, the programmed instruction method was just as effective as the lecture/discussion method in the teaching of reference sources. And students' attitude toward the programmed instruction was favorable enough to secure a continued use of this method for the teaching of reference sources.

• 한국시뮬레이션학회논문지
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• 제12권2호
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• pp.45-53
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• 2003

This paper presents a retargetable compiled assembly simulation technique for fast ASIP(application specific instruction processor) simulation. Development of ASIP which satisfies design requirements in various fields of applications such as telecommunication, wireless network, etc. needs formal design methodology and high-performance relevant software environments such as compiler and simulator In this paper, we employ the architecture description language(ADL) named ${HiXR}^2$ to automatically synthesize an instruction-level compiled assembly simulator. A compiled simulation has benefit of time efficiency to interpretive one because it performs instruction fetching and decoding at compile time. Especially, in case of assembly simulation, instruction decoding is usually a time-consuming job(string operation), so the compiled simulation of assembly simulation is more efficient than that of binary simulation. Performance improvement of the compiled assembly simulation based on ${HiXR}^2$ is exemplified with an ARM9 architecture and a CalmRISC32 architecture. As a result, the compiled simulation is about 150 times faster than interpretive one.

• 대한전자공학회논문지
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• 제27권7호
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• pp.1015-1024
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• 1990

This paper proposes a program counter unit(PCU) on the pipelined architecture of RISC (Reduced Instruction Set Computer) type high performance processors, PCU is used for supplying instruction addresses to memory units(Instruction Cache) efficiently. A RISC processor's PCU has to compute the instruction address within required intervals continnously. So, using the method of self-generated incrementor, is more efficient than the conventional one's using ALU or private adder. The proposed PCU is designed to have the fast +4(Byte Address) operation incrementor that has no carry propagation delay. Design specifications are taken by analyzing the whole data path operation of target processor's default and exceptional mode instructions. CMOS and wired logic circuit technologic are used in PCU for the fast operation which has small layout area and power dissipation. The schematic capture and logic, timing simulation of proposed PCU are performed on Apollo W/S using Mentor Graphics CAD tooks.

• Journal of Multimedia Information System
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• 제8권4호
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• pp.243-250
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• 2021

Instructional contents are used to demonstrate a technical process to teach and walkthrough certain procedures to carry out a task. This type of informational content is widely used for teaching and lectures in form of tutorial videos and training videos. Since there are questions and uncertainties for what could be the killer application for the novel wearables, we propose a self-instruction training application on a smart glass to utilize already-available instruction videos as well as public open data in creative ways. We design and implement a prototype application to help users train by wearing smart glasses specifically designed for two concrete and hand-constrained use cases where the user's hands need to be free to operate. To increase the efficiency and feasibility of the self-instruction training, we contribute to the development of a wearable killer application by integrating a voice-based user interface using speech recognizer, public open data APIs, and timestamp-based procedural content navigation structure into our proof-of-concept application.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 춘계종합학술대회 A
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• pp.281-284
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• 2008

최근 OpenGL ES 2.0이 개정됨에 따라 모바일 기기에 Shader 3.0모델을 지원 가능한 프로세서가 요구된다. 이 쉐이더 3.0 모델의 지원과 관련하여 명령어의 길이의 증가가 필요하고, 이는 메모리 용량의 증가를 초래한다. 본 논문에서는 가변길이 구조와 유닛구조를 채택한 새로운 명령어 구조를 제안한다. 이 명령어 구조는 쉐이더 3.0 모델을 지원하고 명령어 필드 낭비를 줄일 수 있도록 최대 4개의 32비트 유닛 명령어가 가변적으로 조합되어 수행된다.

• 한국컴퓨터정보학회논문지
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• 제18권7호
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• pp.1-10
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• 2013

본 논문에서는 Thumb-2 명령어 집합 구조의 성능을 개선하기 위하여 분기 명령어와 사용 빈도가 높은 명령어를 동시에 실행하는 병렬 분기 명령어 집합을 제시한다. 제시된 기법에서는 16비트 분기 명령어와 사용 빈도가 높은 16비트 LOAD, ADD, MOV, STORE, SUB 명령어를 각각 결합하는 새로운 32비트 명령어를 도입한다. 새로운 명령어의 인코딩 공간을 제공하기 위해 사용 빈도가 낮은 기존 명령어의 레지스터 필드에 사용되는 비트 수를 줄이고 이를 통해 절약된 비트들을 이용하여 병렬 분기 명령어를 인코딩한다. 실험 결과, 제시된 방법은 코드 크기를 증가시키지 않고 전통적인 방식과 비교하여 평균 8.0%의 성능을 향상시킨다.

• 전기전자학회논문지
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• 제12권2호
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• pp.118-123
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• 2008

최근 Khronos에서 OpenGL ES 2.0 API 표준을 배포 하면서 임베디드 시스템의 그래픽 프로세서에서 능률적인 쉐이더 프로그램이 가능하게 되었다. 그 결과 모바일 기기에서도 OpenGL ES 2.0을 지원하는 그래픽 프로세서를 요구하게 되었다. OpenGL ES 2.0을 지원하기 위해서 명령어의 길이의 증가가 요구되고, 이는 메모리 용량의 증가를 초래한다. 본 논문에서는 효율적으로 명령어를 사용하는 새로운 명령어를 제안한다. 이 명령어는 가변 길이 방법과 유닛구조를 채택한 명령어 구조이다. 제안된 명령어 구조는 OpenGL ES 2.0 API를 지원하고 명령어 필드 낭비를 줄일 수 있도록 최대 4개의 32비트 유닛 명령어가 가변적으로 조합되어 수행된다.