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http://dx.doi.org/10.9708/jksci.2013.18.7.001

Parallel Branch Instruction Extension for Thumb-2 Instruction Set Architecture  

Kim, Dae-Hwan (Dept. of Computer Information, Suwon Science College)
Publication Information
Journal of the Korea Society of Computer and Information / v.18, no.7, 2013 , pp. 1-10 More about this Journal
Abstract
In this paper, the parallel branch instruction is proposed which executes a branch instruction and the frequently used instruction simultaneously to improve the performance of Thumb-2 instruction set architecture. In the proposed approach, new 32-bit parallel branch instructions are introduced which combine 16-bit branch instruction with each of the frequently used 16-bit LOAD, ADD, MOV, STORE, and SUB instructions, respectively. To provide the encoding space of the new instructions, the register field in less frequently executed instructions is reduced, and the new instructions are encoded by using the saved bits. Experiments show that the proposed approach improves performance by an average of 8.0% when compared to the conventional approach.
Keywords
Instruction set design; Parallel branch instruction; Embedded processor; Thumb-2; ARM;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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1 Advanced RISC Machines Ltd., "ARM Annual Report & Accounts 2012," Advanced RISC Machines Ltd., 2012.
2 R. Phelan, "Improving ARM Code Density and Performance," Technical report, Advanced RISC Machines Ltd.. June 2003.
3 S. Segars, K. Clarke, and L. Goudge, "Embedded control problems, Thumb, and the ARM7TDMI," IEEE Micro, Vol. 15, No. 5, pp. 22-30, Oct. 1995.
4 J. L. Hennessy, and D. A. Patterson, "Computer Architecture - A Quantitative Approach (5. ed.)," Morgan Kaufmann, pp. 148-261, 2011.
5 J. A. Fisher, P. Faraboschi, and C. Young, "Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools," Elsevier Morgan Kauffman, pp. 45-398, 2005.
6 D. -H. Kim, "AMEX: Extending Addressing Mode of 16-bit Thumb Instruction Set Architecture," Journal of The Korea Society of Computer and Information, Vol. 17, No. 11, pp. 1-10, 2012.   과학기술학회마을   DOI   ScienceOn
7 A. Krishnaswamy and R. Gupta, "Efficient Use of Invisible Registers in Thumb Code," In Proc. of the 38th IEEE/ACMInternational Symposium on Microarchitecture, pp. 30-42, Nov 2005.
8 A. Krishnaswamy, and R. Gupta, "Dynamic coalescing for 16-bit instructions," ACM Transaction on Embedded Computing System, Vol. 4, No. 1, pp. 3-37, Feb. 2005.   DOI
9 Y. -J. Kwon, X. Ma, and H. J. Lee, "PARE: instruction set architecture for efficient code size reduction," IEE Electronics Letters, Vol. 35, No. 24, pp. 2098-2099, Nov. 1999.   DOI   ScienceOn
10 B. Li, and R. Gupta, "Bit Section Instruction Set Extension of ARMfor Embedded Applications," In Proc. of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), pp. 69-78, Grenoble, France, 2002.
11 H.-H. Chiang, H.-J. Cheng, and Y.-S. Hwang, "Doubling the Number of Registers on ARM Processors," In Proc. of the 16th Workshop on Interaction between Compilers and Computer Architectures (INTERACT-16), pp. 1-8, Feb. 2012.
12 Hedley Francis, "ARM DSP-Enhanced Extensions," ARM Ltd., 2001.
13 J. Rokov, and D. Ing, "ARM Architecture and Multimedia Applications," RIZ-Transmitters Co., 2010.
14 ARM Ltd. "Introducing NEON$^{TM}$ Development Article," 2009.
15 J. Goodacre, and A. N. Sloss, "Parallelism and the ARM instruction set architecture," Computer, Vol. 38, No. 7, pp. 42-50, 2005.   DOI
16 D. -H. Kim, "The Compressed Instruction Set Architecture for the OpenRISC Processor," Journal of The Korea Society of Computer and Information, Vol. 17, No. 10, pp. 11-23, 2012.   과학기술학회마을   DOI   ScienceOn
17 F. Bellard, "QEMU, a fast and portable dynamic translator," In Proc. of the Int. Conf. on USENIX Annual Technical Conference, Berkeley, CA, USA, pp. 41-41, 2005.
18 ARM, "Cortex-M3 technical reference manual," http://www.arm.com, 2010.