• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.33-40
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• 2008

As the speed of memory is improved vey fast the advanced test equipments are needed to test the ultra-high speed memory devices efficiently. It is necessary to develop the Algorithmic Pattern Generator (ALPG) that tests fast memory devices effectively using the instructions that testers want to use. In this paper, we propose a new parallel ALPG for the ultra-high speed memory testing. The proposed ALPG can generate patterns for fast memory devices at high speed using manual instructions by the Instruction Analyzer.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.97-105
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• 2016

Microcontrollers (MCUs) for endpoint smart sensor devices of internet-of-thing (IoT) are being implemented as system-on-chip (SoC) with on-chip instruction flash memory, in which user firmware is embedded. MCUs directly fetch binary code-based instructions through bit-line sense amplifier (S/A) integrated with on-chip flash memory. The S/A compares bit cell current with reference current to identify which data are programmed. The S/A in reading '0' (erased) cell data consumes a large sink current, which is greater than off-current for '1' (programmed) cell data. The main motivation of our approach is to reduce the number of accesses of erased cells by binary code level transformation. This paper proposes a built-in write/read path architecture using binary code inversion method based on hot-spot region detection of instruction code access to reduce sensing current in S/A. From the profiling result of instruction access patterns, hot-spot region of an original compiled binary code is conditionally inverted with the proposed bit-inversion techniques. The de-inversion hardware only consumes small logic current instead of analog sink current in S/A and it is integrated with the conventional S/A to restore original binary instructions. The proposed techniques are applied to the fully-custom designed MCU with ARM Cortex-M0$^{TM}$ using 0.18um Magnachip Flash-embedded CMOS process and the benefits in terms of power consumption reduction are evaluated for Dhrystone$^{TM}$ benchmark. The profiling environment of instruction code executions is implemented by extending commercial ARM KEIL$^{TM}$ MDK (MCU Development Kit) with our custom-designed access analyzer.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.203-206
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• 2005

This paper presents a design experience of supervisory control system for agile and intelligent manufacturing(AIM). For effectively program job instructions, a Petri net-type graphical language is proposed and it can be applied to a various task such as concurrency and synchronization. PGL is consisted of PGL editor, PGL analyzer and PGL translator; PGL editor generates a job instruction program using graphic symbol. PGL analyzer prevents a deadlock or resource allocation of unit cell. PGL translator transfers to adequate sequential job commands of each unit cell.

• Journal of Korean Society on Water Environment
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• v.37 no.6
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• pp.449-457
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• 2021

Photosynthesis and respiration rate of microalgae are important factors during advanced wastewater treatment research using microalgae, There are several equipments and measurement methods for measuring photosynthesis and respiration, with different challenges that occur during pretreatment and stabilization of the analysis process. Therefore, in this study, for accurate Photosynthesis and Respiration (P&R) analyzer measurement, the analysis process was divided into pre-processing, DO stabilization, and analysis stages and each was optimized to enable accurate evaluation. For this purpose, the effect of DO saturation of the sample on P&R analysis, DO stabilization according to the degassing flow rate, and photoinhibition of the OD level on photosynthesis was investigated. Based on our study results, when DO was supersaturated, photosynthetic efficiency decreased due to photorespiration, making it inappropriate as a P&R sample. In addition, 0.5 L-N2/min level was the optimal nitrogen degassing flow rate for DO desaturation. The inhibition of photosynthetic efficiency by self-shading caused by the increase in OD was observed from OD 2.0, and it was found that P& R analysis is preferably performed on samples with OD less than 2.0. In addition, based on the above three optimization results, an optimized P&R Analyzer instruction for accurate P&R analysis was also presented.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.5
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• pp.115-121
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• 2023

RISC-V is an open-source instruction set architecture, and anyone can freely design and implement a RISC-V microprocessor. This paper designes and simulates the RISC-V architecture, synthesizing it in FPGA and verifying it using logic analyzer (ILA). RISC-V core is written in SystemVerilog, which has efficient design and high reusability, and can be used in various application fields. The RISC-V core is implemented as hardware by synthesizing it on the Ultra96-V2 FPGA board using Vivado, and the accuracy and operation of the design are verified through Integrated Logic Analyzer(ILA). As a result of the experiment, it is confirmed that the designed RISC-V core performs the expected operation, and these results can contribute to the design and verification of RISC-V based systems.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10c
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• pp.691-693
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• 2002

슈퍼스칼라 프로세서 구조에서 명령어 실행을 수행하는 데 사용되는 자원은 그 양에 비해 실제로 활용된 자원의 양은 적다. 본 논문에서는 낮은 자원활용도를 보이는 자원을 활용하는 방안으로 슈퍼스칼라 프로세서를 멀티쓰레드 프로세서로 확장하는데 필요한 기본 데이터를 얻기 위해서 실제로 활용되는 자원의 양을 측정하여 어느 정도의 자원을 활용할 수 있는 지와 자원이 충분히 활용되지 못하는 원인을 분석하였다. 실험을 위해 RA(Resource Analyzer)를 구현하여 SimpleScalar 시뮬레이터에서 제공되는 명령어 파이프라인 트레이스 파일을 분석하여 각 파이프라인 단계에서 처리되는 자원의 활용도를 실험하였다. 자원 활용도가 낮은 원인을 분석하기 위해 프로그램 내에 존재하는 데이터 의존성과 여러 가지 미스 요인들의 비율을 실험을 통해 알아본 결과 IPC(Instruction Per Cycle)는 평균 0.6으로 나타났으며, EX단계의 평균 활용 빈도는 22.9%로 낮아 멀티쓰레드 처리의 필요성이 있음을 확인할 수 있었다.

• Journal of Computing Science and Engineering
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• v.5 no.2
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• pp.131-140
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• 2011

Different cores typically share the last-level cache in a multi-core processor. Threads running on different cores may interfere with each other. Therefore, the multi-core worst-case execution time (WCET) analyzer must be able to safely and accurately estimate the worst-case inter-thread cache interference. This is not supported by current WCET analysis techniques that manly focus on single thread analysis. This paper presents a novel approach to analyze the worst-case cache interference and bounding the WCET for threads running on multi-core processors with shared L2 instruction caches. We propose to use an interference matrix to model inter-thread interference, on which basis we can calculate the worst-case inter-thread cache interference. Our experiments indicate that the proposed approach can give a worst-case bound less than 1%, as in benchmark fib-call, and an average 16.4% overestimate for threads running on a dual-core processor with shared-L2 cache. Our approach dramatically improves the accuracy of WCET overestimatation by on average 20.0% compared to work.

• Proceedings of the Korean Society of Computer Information Conference
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• 2018.07a
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• pp.466-469
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• 2018

최근 PC를 비롯한 모바일, IOT 기기 등 다양한 환경에서의 사이버 공격이 기승을 부리고 있으며, 그 방법 또한 나날이 발전하고 있다. 이러한 사이버위협으로부터 개인 및 기업의 자산을 지키기 위한 근본적인 대안이 없이는 매번 반복적인 피해를 피하기 어려운 현실이다. 다양한 환경이라고 함은, 다양한 OS(Operation System), 다양한 ISA (Instruction Set Architecture)의 조합으로 이루어지는 사이버환경을 의미한다. 이러한 조합들은 일반 사용자들에게 가장 많이 쓰이는 Windows & Intel 조합의 환경과, Linux & Intel 또는 Linux & ARM 등 기업에서 서비스를 위해 쓰이는 서버 환경 등을 예로 들 수 있다. 그밖에 최근 IOT기기나 모바일 기기와 같은 환경도 있을 수 있다. 바이너리 파일에 대한 보안은 다양한 연구가 진행되고 있지만 그 범위가 방대하고, 깊이가 필요한 영역이라 진입 장벽이 높은 실정이다. 본 논문에서는 이러한 바이너리의 취약점을 분석하기 위한 첫 번째 단계로써 다양한 바이너리 파일을 하나의 정형화된 자료구조로 변환하는 바이너리 포맷 분석기의 한 방법을 제시하고자 한다. 다양한 OS와 다양한 ISA환경에서 사용되는 바이너리들에서 공통적으로 존재하는 정보들 중, 바이너리의 취약점 분석을 위해 필요한 데이터를 보다 효율적으로 수집하고, 관리하는 것이 바이너리를 통한 사이버 위협을 탐지하는 연구에서 기초가 된다고 할 수 있기 때문이다.

• The KIPS Transactions:PartA
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• v.18A no.3
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• pp.109-114
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• 2011

We describe a technique for automatically proving compiler optimizations sound, meaning that their transformations are always semantics-preserving. As is well known, IR (Intermediate Representation) optimization is an important step in a compiler backend. But unfortunately, it is difficult to detect and debug the IR optimization errors for compiler developers. So, we introduce a C level error check system for detecting the correctness of these IR transformation techniques. In our system, we first create an IR-to-C converter to translate IR to C code before and after each compiler optimization phase, respectively, since our technique is based on the Memory Comparison-based Clone(MeCC) detector which is a tool of detecting semantic equivalency in C level. MeCC accepts only C codes as its input and it uses a path-sensitive semantic-based static analyzer to estimate the memory states at exit point of each procedure, and compares memory states to determine whether the procedures are equal or not. But MeCC cannot guarantee two semantic-equivalency codes always have 100% similarity or two codes with different semantics does not get the result of 100% similarity. To increase the reliability of the results, we describe a technique which comprises how to generate C codes in IR-to-C transformation phase and how to send the optimization information to MeCC to avoid the occurrence of these unexpected problems. Our methodology is illustrated by three familiar optimizations, dead code elimination, instruction scheduling and common sub-expression elimination and our experimental results show that the C level error check system is highly reliable.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.35 no.10
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• pp.940-947
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• 2007

For the performance upgrade of a supersonic jet fighter, the processor and FLCC(Flight Control Computer) Architecture were upgraded from a baseline FLCC. Prior to the hardware implementation phase, the exact CPU throughput estimation is necessary. For this purpose, an experimental method for new FLCC throughput estimation was introduced in this study.　While baseline FLCC operating, the CPU address bus was collected with logic analyzer, and then decoded to get the exact access times to each memory-memory and the number of program Instruction branches. Based on these data, a throughput test in CPU demo-board of the new FLCC configuration was performed. From test results, the CPU-Memory architecture was design-changed before FLCC hardware implementation phase. To check the flight stability degradation due to power-interrupt problem due to CPU-Memory architecture change, the piloted HILS (Hardware-In-the Loop Simulator) test was conducted.