• Journal of Internet Computing and Services
• /
• v.8 no.5
• /
• pp.161-170
• /
• 2007

The proposed switch which has separated data plane and switching plane can make parallel processing for packet data storing, memory address pointer switching and simultaneously can be capable of switching the variable length for IP packets. The proposed architecture does not require the complicated arbitration algorithms in VOQ, also is designed for QoS of generic output queue switch as well as input queue. At the result of simulations, the proposed architecture has less average packet delay than the one of the memory-sharing based architecture and guarantees keeping a certain average packet delay in increasing switch size.

• Journal of applied mathematics & informatics
• /
• v.16 no.1_2
• /
• pp.469-481
• /
• 2004

In this paper, we investigate the mean queue length and the mean packet delay of a dynamic bandwidth allocation(DBA) scheme in an Ethernet passive optical network(EPON). We focus on the interleaved polling system with a gated service discipline. We assume that input packets arrive at an optical network unit(ONU) according to Poisson process. We use a continuous time queueing model in order to find the queue length distribution of the gated interleaved polling system with the first stage input queue and the second stage transmission queue. We give some numerical results to investigate the mean queue lengths and mean packet delays for the symmetric polling system with statistically identical stations.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.6
• /
• pp.9-17
• /
• 1994

ATM (Asynchronous Transfer Mode) has a fixed-length packet transport scheme. It is one of the promising proposals in B-ISDN.Since the packet length is fixed, it can be potentially to perform the various service to users. In this paper, a queueing model for an ATM multip`exer loaded by CBR and ON/OFF input sources is considered, and the two-queue system which each type of input sources has a queue with a finite capacity is analyzed. The cell loss probabilities for a performance measures of ATM multiplexer are derived, and are also evaluated through numerical examples. As a result, the cell loss probability of ON/OFF sources for the queue size is rapidly decreased when the multiplexed number and burstiness are increased. Since cells of the CBR source have lower priority than cells of the ON/OFF source, cell loss probabilities of CBR sources are accordingly high independently of CBR cell arrival rate when the number of CBR sources is large.

• Journal of Korean Institute of Industrial Engineers
• /
• v.27 no.1
• /
• pp.89-94
• /
• 2001

There are many queueing systems where customers wait for service up to a certain amount of time and leave the system if they are not served during that time. This paper considers a finite capacity multi-server queueing system with Poisson input and Erlang service time, where a customer becomes a lost customer when his service has not begun within an exponential patient time after his arrival. Performance measures such as average queue length, the average number of customers in service, and the proportion of lost customers can be obtained exactly through the proposed numerical solution procedure.

• Journal of the Korean Society for Industrial and Applied Mathematics
• /
• v.17 no.2
• /
• pp.103-113
• /
• 2013

We analyze the queueing model for leaky bucket (LB) scheme with dynamic arrivals and token rates. In other words, in our LB scheme the arrivals and token rates are changed according to the buffer occupancy. In telecommunication networks, the LB scheme has been used as a policing function to prevent congestion. By considering bursty and correlated properties of input traffic, the arrivals are assumed to follow a Markov-modulated Poisson process (MMPP). We derive the distribution of system state, and obtain the loss probability and the mean waiting time. The analysis is done by using the embedded Markov chain and supplementary variable method. We also present some numerical examples to show the effect of our proposed model.

• Journal of Korean Society of Industrial and Systems Engineering
• /
• v.30 no.1
• /
• pp.33-40
• /
• 2007

A multi-server queueing system with finite buffer is considered. The input flow is the BMAP (Batch Markovian Arrival Process). The service time has the PH (Phase) type distribution. Customers from the BMAP enter the system according to the discipline of partial admission. Besides ordinary (positive) customers, the Markovian flow (MAP) of negative customers arrives to the system. A negative customer can delete an ordinary customer in service if the state of its PH-service process belongs to some given set. In opposite case the ordinary customer is considered to be protected of the effect of negative customers. The stationary distribution and the main performance measures of the considered queueing system are calculated.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.1A
• /
• pp.122-131
• /
• 2000

In this paper, we propose a cell scheduling algorithm for input queueing ATM switch. The input queueing architecture is attractive for building an ultra-high speed ATM (Asynchronous Transfer Mode) switch. We proposea WMUCS (Weighted Matrix Unit Cell Scheduler) based on the MUCS which resolves HOL blocking and outputport contention. The MUCS algorithm selects an optimal set of entries as winning cells from traffic matrix (weightmatrix). Our WMUCS differs from the MUCS in generating weight matrices. This change solves the starvationproblem and it reduces the cell loss variance. The performance of the proposed algorithm is evaluated by thesimulation program written in C++. The simulation results show that the maximum throughput, the average celldelay, and the cell loss rate are significantly improved. We can see that the performance of WMUCS is excellentand the cost-effective implementation of the ATM switch using proposed cell scheduling algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.4
• /
• pp.812-822
• /
• 1997

In this paper, we propose an architecture of the asynchronous shared-bus type switch with priority and fairness schemes. The switch architecture is an input and output queueing system, and the priority scheme is implemented in both input and output queues. We analyze packet delay of both input and output queues. In the analysis, we consider to stations with asymmetric arrival rates. Although we make some approximations in the analysis, the numerical results show good agreements with the simulation results.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.1A
• /
• pp.114-121
• /
• 2000

The problem of an input-buffered switch is the HOL(head-of-line) blocking which limits the maximum throughput but it is easy to implement in hardware. However, HOL blocking can be eliminated using aVOQ(virtual-output-queueing) technique. 0 this paper, we propose a new cell-scheduling algorithm for aninput-buffered ATM switch. The proposed algorithm, called PPIM(Probabilistic Parallel Iterative Matching), imposesa weight to every request based on the reserved bandwidth. It is shown that the input-buffered ATM switch withthe proposed PPIM algorithm not only provides high throughput and low delay but it also reduces the jitter,compared with the existing WPIM(Weighted PIM).

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.23 no.5
• /
• pp.1184-1195
• /
• 1998

In this paper, we compare vaious input-buffered ATM switch architectures in structures on input buffer and switching fabric, the resons for performance improvement and degradation, arbitration scheme and maximum throughput, and present comparative merits and demerits of each architecture under random and bursty traffic. We also analyze the prformance of combined architectures of windowing scheme, destination-queueing based input-port expansion schemeand output-port expansion scheme, and show that it is possible to achieve 100% throughput with combined scheme of destination-queueing based input-port expansion scheme and output-port expansio scheme when the number of output group is 2 and output port expansion ratio is 2.