• Journal of Power Electronics
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• 제13권1호
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• pp.20-30
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• 2013

This paper presents a soft switching DC/DC converter for high voltage application. The interleaved pulse-width modulation (PWM) scheme is used to reduce the ripple current at the output capacitor and the size of output inductors. Two converter cells are connected in series at the high voltage side to reduce the voltage stresses of the active switches. Thus, the voltage stress of each switch is clamped at one half of the input voltage. On the other hand, the output sides of two converter cells are connected in parallel to achieve the load current sharing and reduce the current stress of output inductors. In each converter cell, a half-bridge converter with the asymmetrical PWM scheme is adopted to control power switches and to regulate the output voltage at a desired voltage level. Based on the resonant behavior by the output capacitance of power switches and the transformer leakage inductance, active switches can be turned on at zero voltage switching (ZVS) during the transition interval. Thus, the switching losses of power MOSFETs are reduced. The current doubler rectifier is used at the secondary side to partially cancel ripple current. Therefore, the root-mean-square (rms) current at output capacitor is reduced. The proposed converter can be applied for high input voltage applications such as a three-phase 380V utility system. Finally, experiments based on a laboratory prototype with 960W (24V/40A) rated power are provided to demonstrate the performance of proposed converter.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 B
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• pp.980-982
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• 2002

In this paper, we report the experimental results of the Forward-flyback DC-DC converter with current doubler and synchronous rectifier. The experimental converter, that has a output voltage 1.8V, output current 25A, maximum power of 45W, switching frequency of 290kHz and input voltage range of 36-75V, has been successfully implemented. As a result, in the entire voltage range the measured full load efficiency was above 82%, and the output voltage was regulated at 1.8V within ${\pm}$3% tolerance.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 B
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• pp.1006-1007
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• 2006

An active-clamp current-fed push-pull converter for the step-up application is proposed. The proposed converter is composed of active-clamp circuits and a voltage doubler rectifier. Thus, the voltage stress of the main switches is reduced and the output diodes are clamped to output voltage. Moreover, the output diodes can achieve zero current switching (ZCS) by the series resonance between resonant capacitors and leakage inductances. The prototype is designed for 350V/1.5kW with input voltage range $30{\sim}60V$. The theoretical analysis and experimental results are presented.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제49권8호
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• pp.551-556
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• 2000

A zero-voltage-switching(ZVS) programmable power supply employing the ZVS active clamp forward converter is suggested. Through the analysis on operation region of the supply, the constant power region and the maximum current limit region are clearly identified. Furthermore, the duty ratio range corresponding to the variation range of the output voltages and the control scheme at the minimum duty ration region are presented. Finally, in order to vefity the validity of the operation for the proposed power supply, experimental evaluation results obtained on an 1kW prototype power supply for the 198~242VAC input voltage range(220VAC$\pm$10%), the 0~25V output voltage range, and the 100kHz switching frequency are presented.

• 한국항행학회논문지
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• 제15권4호
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• pp.596-601
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• 2011

본 논문에서는 간단한 회로구조와 높은 효율을 갖는 스위칭 방식의 E급 주파수 체배기에 대한 연구를 수행하였다. 주파수 체배는 능동소자의 비선형성에 의해 발생하는데 본 논문에서는 FET 능동소자를 간단한 스위치 및 기생소자 성분 모델로 근사하여 특성을 해석하고자 하였다. FET를 입력에 의해 동작하는 스위치 및 기생소자로 모델링하고 E급 주파수 체배기의 정합소자 값을 유도하였다. ADS시뮬레이터를 이용하여 출력 전압과 전류 파형 및 효율을 시뮬레이션하고 기생성분에 따른 변화를 연구하였다. 기생 커패시턴스, 저항, 인덕턴스에 의한 영향을 시뮬레이션하였으며 입력주파수 2.9GHz, 바이어스전압 2V일 때, 출력주파수 5.8GHz에서 기생커패시턴스가 0pF에서 1pF으로 변화함에 따라 드레인효율은 98%에서 28%로 감소하여 기생커패시턴스 CP가 FET의 기생 성분 중 가장 큰 영향을 끼친 것을 확인했다.

• 전력전자학회논문지
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• 제18권6호
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• pp.515-522
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• 2013

In this paper, a new PCS is proposed which is consisted of high boost dual converter and single phase half-bridge inverter. The proposed PCS is configured in parallel input / serial output, using two interleaved voltage doubler converter. Converter of the proposed PCS is distribute input current by configuring parallel input and reduced turn ratio of transformer by configuring serial output. Also, compositions of the inverter are composed of serial output capacitor of converter and half-bridge inverter. The dual converter and single phase half-bridge inverter is designed and characteristic of the new PCS is analysed. The system of the 1.5[kW] PCS is verified through an experimental about operation and stability.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.1322-1327
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• 2005

This paper presents a single-stage ZVT full-bridge AC/DC converter for aerospace applications. The detailed operating principle and design consideration of this soft-switched converter are analyzed and described. The proposed circuit topology and control scheme are proposed to exhibit optimum performances (i.e. high power factor, high efficiency, ring-free and low EMI features). A laboratory prototype, 500W 5V/100A AC/DC converter was implemented. The simulation and experimental waveforms verify the feasibility of the proposed design.

• 한국전자통신학회논문지
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• 제11권1호
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• pp.65-72
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• 2016

본 논문에서 풀브리지 컨버터와 2차측은 전류더블러로 구성되어 있는 차량용 양방향 LDC를 개발하였다. LDC는 한쪽의 DC입력을 다른쪽의 DC 출력으로 변환시키는 컨버터이며, 본 논문에서 개발된 컨버터는 양방향으로 전력전달이 가능하다. 개발된 LDC는 1400W에서 90%의 효율을 보이고 2KW에서 약 85%정도의 효율을 나타내는 것이 확인되었다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2007년도 하계학술대회 논문집
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• pp.238-240
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• 2007

A new ZVZCS Single-Stage Power-Factor-Correction(PFC) AC/DC converter with boost PFC cell is integrated with voltage doubler rectified asymmetrical half-bridge(VDRAHB) is proposed in this paper. The proposed converter features good power factor correction, low current harmonic distortions, tight output regulations and low voltage of link capacitor. An 85W prototype was implemented to show that it meets the harmonic requirements and standards satisfactorily with nearly unity power factor and high efficiency over universal input.

• Journal of Power Electronics
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• 제12권3호
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• pp.377-386
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• 2012

An interleaved bridgeless buck-boost AC/DC converter is presented in this paper to achieve the characteristics of low conduction loss, a high power factor and low harmonic and ripple currents. There are only two power semiconductors in the line current path instead of the three power semiconductors in a conventional boost AC/DC converter. A buck-boost converter operated in the boundary conduction mode (BCM) is adopted to control the active switches to achieve the following characteristics: no diode reverse recovery problem, zero current switching (ZCS) turn-off of the rectifier diodes, ZCS turn-on of the power switches, and a low DC bus voltage to reduce the voltage stress of the MOSFETs in the second DC/DC converter. Interleaved pulse-width modulation (PWM) is used to control the switches such that the input and output ripple currents are reduced such that the output capacitance can be reduced. The voltage doubler topology is adopted to double the output voltage in order to extend the useable energy of the capacitor when the line voltage is off. The circuit configuration, principle operation, system analysis, and a design example are discussed and presented in detail. Finally, experiments on a 500W prototype are provided to demonstrate the performance of the proposed converter.