• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.261-267
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• 2001

This paper presents the architecture of multiple-queue manager for input-queued switch, which has arbitration latency, and the design of the chip. The proposed architecture of multiple-queue manager provides wire-speed routing with a pipelined buffer management, and the tolerance of requests and grants data transmission latency between the input queue manager and central arbiter using a new request control method, which is based on a high-speed shifter. The multiple-input-queue manager has been implemented in a field programmable gate array chip, which provides OC-48c port speed. It enhances the maximum throughput of the input queuing switch up to 98.6% with 128-cell shared input buffer in 16$\times$16 switch size.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.271-275
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• 2005

Queueing models are good models for fragments of communication systems and networks, so their investigation is interesting for theory and applications. Theses queues may play an important role for the validation of different decomposition algorithms designed for investigating more general queueing networks. So, in this paper we illustrate that the batch size distribution affects the loss probability, which is the main performance measure of a finite buffer queues.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.243-246
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• 2002

This paper presents a study on the design and implementation of modulized I/O buffer control system for large capacity cable check. A 8bit I/O buffer basic module which has feedback loops with input and output buffers is simulated in PSpice and implemented with logic gates. This system is composed of 18 sub-boards which have 3 channels of 32bit data buses, and of a main board with MPC860 microprocessor.

• Journal of Korea Society of Industrial Information Systems
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• v.11 no.1
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• pp.1-6
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• 2006

Queueing models are good models for fragments of communication systems and networks, so their investigation is interesting for theory and applications. Theses queues may play an important role for the validation of different decomposition algorithms designed for investigating more general queueing networks. So, in this paper we illustrate that the batch size distribution affects the loss probability, which is the main performance measure of a finite buffer queues.

• Journal of Electrical Engineering and information Science
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• v.3 no.2
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• pp.274-279
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• 1998

We investigate a Leaky Bucket(LB) scheme with a threshold in the data buffer, where leaky rate changes depending on the contents of data buffer. We use the fluid flow model for the analysis of the LB scheme with a threshold. We model the bursty input source as markov modulated fluid flow(MMFF) As performance measures we obtain loss probability and mean delay. We present some numerical results to show the effects of the level of a threshold, the rate of token generation, the size of token pool, and the size the data buffer on the performances of the LB scheme with a threshold.

• Journal of the Korean Operations Research and Management Science Society
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• v.21 no.3
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• pp.47-61
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• 1996

An ATM switch must deal with various kinds of input sources having different traffic characteristics and it must guarantee very small value of cel loss probability, about 10$^{8}$ -10$^{12}$ , to deal with loss-sensitive traffics. In order to estimate such a rate event probability with simulation procedure, a variance reduction technique is essential for obtaining an appropriate level of precision with reduced cost. In this paper, we propose a hybrid simulation technique to achieve reduction of variance of cell loss probability estimator, where hybrid means the combination of analytical method and simulation procedure. A discrete time queueing model with multiple input sources and a finite shared buffer is considered, where the arrival process at an input source and a finite shared buffer is considered, where the arrival process at an input source is governed by an Interrupted Bernoulli Process and the service rate is constant. We deal with heterogeneous input sources as well as homogeneous case. The performance of the proposed hybrid simulation estimator is compared with those of the raw simulation estimator and the importance sampling estimator in terms of variance reduction ratios.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.291-294
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• 2004

In this paper, we consider the broadcast switch architecture for hish performance multicast packet switching. In input and output buffered switch, we propose a new switch architecture which supports high throughput in broadcast packet switching with switch planes of single input and multiple output crossbars. The proposed switch architecture has a central arbiter that arbitrates requests from plural input ports and generates multiple grant signals to multiple output ports in a packet transmission slot. It provides high speed pipelined arbitration and large scale switching capacity.

• Journal of the Korea Institute of Military Science and Technology
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• v.5 no.2
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• pp.103-115
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• 2002

This paper describes the results on the design and implementation of large capacity cable checking system using I/O buffer method. The I/O buffer module which has feedback loops with input and output buffers is designed with logic gate in the VME board and controlled by MPC860 microprocessor. So this system can check a lot of cable at the same time with less size and less processing time than that of relay matrix method with the A/D converter. The size of the I/O buffer module can be variable according to the number of cable. And any type of cable can be checked even if the pin assignment of cable is changed.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.108-116
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• 2013

The input buffer in Network on Chip (NoC) router plays a key role in on-chip-network performance, which is utilized in flow control and virtual channel. However, increase in area and power due to input buffers as the network size gets larger is becoming severe. To solve this problem, a bufferless deflection routing without input buffer was suggested. Since the bufferless deflection routing shows poor performance at high network load, other approaches which combine the deflection routing with small size side buffers were also proposed. Nonetheless these new methods still show deficiencies caused by frequent path collisions. In this paper, we propose a modified deflection routing technique using a location based priority. In comparison with existing deflection routers, experimental results show improvement by 12% in throughput with only 3% increase in area.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1992.04b
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• pp.261-261
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• 1992