• 제목/요약/키워드: Information architecture

Search Result 9,318, Processing Time 0.035 seconds

Distributional Patterns and the Evaluation of Hydrophytic Plants of Urban Wetlands in Seongnam City, Gyunggi-do Province, Korea (경기도 성남시 도시지역 습지의 유형 분포 및 습지식물의 특성 평가)

  • Chun, Seung-Hoon
    • Korean Journal of Environment and Ecology
    • /
    • v.22 no.2
    • /
    • pp.159-172
    • /
    • 2008
  • This study was carried out to obtain ecological information necessary for a conservation plan based on the distributional patterns, wetland types, and hydrophytic characteristics of urban wetlands in Seongnam City, Kyunggi Province where representing the various patterns of land use made by rapid urbanization since 1970s. Total 162 sites of four wetland types were identified as urban wetlands during the first survey. The sites were classified into 55 forested swamps, 4 riverine wetlands, 62 abandoned paddy fields, 37 small ponds, and 4 reservoirs, etc. The second survey targeted 107 sites which were identified as good wetlands. It showed that 42 sites(about 39%) were already degraded due to drainage, landfill, and crop cultivation at 6 months intervals. Both hydrologic conditions and hydrophytic characteristics of 27 good wetlands help maintain current ecological status, but most wetlands have been degraded by artificial impacts. Among 184 species identified, only 75 species(about 40.7%) were hydrophytes. Prevalence Index of hydrophyte based on three categories of OBL(obligatory wetland plant), FAC(facultitative plant), UPL(obligatory upland plant) was 3.7, indicating that vegetation data alone is inadequate to designate as wetlands. This study revealed that as critical habitats for wildlife they playa vital role in ecotone between both terrestrial and aquatic ecosystem with its proper distributional pattern in spite of their small areas compared to the entire geographic region of the City.

A Study on the Casual Wear Design based on the Image of the Modernized Korean Costume (생활한복 이미지를 활용한 캐주얼웨어 디자인 개발)

  • Park Young-Seon
    • Journal of the Korean Society of Costume
    • /
    • v.55 no.1 s.91
    • /
    • pp.25-42
    • /
    • 2005
  • Costume is a formative art expressed by active human unlike the field of other living formativeness, and an expression of social actions based on a style of culture in a period. Therefore, costume has a deep connection with a mode of living and is recognized as a 'culture for living', and is more characteristic culture than all metaphysical cultures including architecture, craft, painting, and sculpture. Therefore, it expresses wearer's status or social standing, and furthermore, ideas and values of the times with aesthetic features in their form, color, materials, and pattern, so it is expressed as a mirror reflecting the phases of the times as. Korean costume had been dressed until the period of the Joseon Dynasty without a great change and started to be simplified in a simple style on the grounds of inconvenience in behaviors with the opening of an interchange of Western culture in the civilized period. And, this movement had been continued and Korean costume had been applied as an everyday dress under the name of 'Reformed Korean Costume'. Since the middle phase of 1980s, it aroused many people's interests with the introduction of designs focused on activity and convenience. In 1990's, many people had taken a growing interest in Korean costume with development of various designs keeping pace with the internationalization period and Korean Costume had been revitalized under the name of 'The Modernized Korean Costume'. And, since the 21st century, the advanced communication and full-scaled import of Western fashion have made the introduction of many fashion information in the world into Korea, affected greatly the fashion market, led consumers' sensitivity on a trend to be increased. Therefore, a design accepting a trend 'The Modernized Korean Costume' with fashions has risen. Second, this study is an attempt to suggest a revitalization method of domestic casual Korean costume brands by developing and suggesting competitive and highly value-added products with connection of practicality, variety, and highly sensitive fashion styles. For theoretical study, domestic and foreign literatures, academic journals, professional monthly magazines, and newspapers were examined. And, a process of change and features of the Korean fashion since the civilization period, and concept, features and images of casual Korean costume were analyzed, On the basis of analyzing image, features, and consumers' preference of the modernized Korean costume, a design development plan was established and 10 suits of costume were designed and made.

Implementation of Smartphone Adaptor for Real-Time Live Simulations (실시간 Live 시뮬레이션을 위한 스마트폰 연동기 구현)

  • Kim, Hyun-Hwi;Lee, Kang-Sun
    • Journal of the Korea Society for Simulation
    • /
    • v.22 no.1
    • /
    • pp.9-20
    • /
    • 2013
  • Defense M&S for weapons effectiveness is a realistic way to support virtual warfare similar to real warfare. As the war paradigm becomes platform-centric to network-centric, people try to utilize smartphones as the source of sensor, and command/control data in the simulation-based weapons effectiveness analysis. However, there have been limited researches on integrating smartphones into the weapon simulators, partly due to high modeling cost - modeling cost to accomodate client-server architecture, and re-engineering cost to adapt the simulator on various devices and platforms -, lack of efficient mechanisms to exchange large amount of simulation data, and low-level of security. In this paper, we design and implement Smartphone Adaptor to utilize smartphones for the simulationbased weapons effectiveness analysis. Smartphone Adaptor automatically sends sensor information, GPS and motion data of a client's smartphone to a simulator and receives simulation results from the simulator on the server. Also, we make it possible for data to be transferred safely and quickly through JSON and SEED. Smartphone Adaptor is applied to OpenSIM (Open simulation engine for Interoperable Models) which is an integrated simulation environment for weapons effectiveness analysis, under development of our research team. In this paper, we will show Smartphone Adaptor can be used effectively in constructing a Live simulation, with an example of a chemical simulator.

Vegetation Structure of Warm Temperate Evergreen Forest at Ch'omch'alsan, Chimdo, Korea (진도 첨찰산 상록활엽수림의 식생구조)

  • Oh, Koo-Kyoon;Cho, Woo
    • Korean Journal of Environment and Ecology
    • /
    • v.10 no.1
    • /
    • pp.66-75
    • /
    • 1996
  • To propose basic information for national resource management and planting disign, plant community structure of evergreen broad-leaved forest was investigated. Fifty-two plots(each size 300m$^{2}$) were set up at Ch'omch'alsan area of Chindo, Korea. TWINSPAN and DCA methods were used for classification and ordination analysis. Fifty-two plots were divided into seven groups, which were Quercus variabilis-Carpinus tschonoskii community, Q. glauca community, Castanepsis cuspidata var. sieboldii-Q. stenophylla community, Castanopsis cuspidata var. sieboldii-Camelia japonica community, Q. acuta-Camelia japonica community, Carpinus coreaca-Q spp. community, C. coreana community. Pinus densiflora almost have been selected. Carpinus tschomoskii, Q. variabillis and Q. serrata were to be succeeded by Castanea cuspidata var. sieboldii, Q. stenophylla, Q. acuta and Neolitsea sericea in canopy layer. And Neolitsea sericea, Q. glauca and Camellia japonica was showed high importance values in fertile soil condition. Future restoration plan was necessary for a tourist resort or national forest in warm temperate region. And evergreen broad-leaved plants shall be planted in considering of environmental condition at warm temperate and industrial complex area.

  • PDF

A 10-bit 100 MSPS CMOS D/A Converter with a Self Calibration Current Bias Circuit (Self Calibration Current Bias 회로에 의한 10-bit 100 MSPS CMOS D/A 변환기의 설계)

  • 이한수;송원철;송민규
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.40 no.11
    • /
    • pp.83-94
    • /
    • 2003
  • In this paper. a highly linear and low glitch CMOS current mode digital-to-analog converter (DAC) by self calibration bias circuit is proposed. The architecture of the DAC is based on a current steering 6+4 segmented type and new switching scheme for the current cell matrix, which reduced non-linearity error and graded error. In order to achieve a high performance DAC . novel current cell with a low spurious deglitching circuit and a new inverse thermometer decoder are proposed. The prototype DAC was implemented in a 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. Experimental result show that SFDR is 60 ㏈ when sampling frequency is 32MHz and DAC output frequency is 7.92MHz. The DAC dissipates 46 mW at a 3.3 Volt single power supply and occupies a chip area of 1350${\mu}{\textrm}{m}$ ${\times}$750${\mu}{\textrm}{m}$.

A Design of an Automatic Current Correcting Charge-Pump using Replica Charge Pump with Current Mismatch Detection (부정합 감지 복제 전하 펌프를 이용한 자동 전류 보상 전하 펌프의 설계)

  • Kim, Seong-Geun;Kim, Young-Shin;Pu, Young-Gun;Park, Joon-Sung;Hur, Jeong;Lee, Kang-Yoon
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.47 no.2
    • /
    • pp.94-99
    • /
    • 2010
  • This paper presents a charge pump architecture for correcting the current mismatch due to the PVT variation. In general, the current mismatch of the charge pump should be minimized to improve the phase noise and spur performance of the PLL. In order to correct the current mismatch of the charge pump, the current difference is detected by the replica charge pump and fed back into the main charge pump. This scheme is very simple and guarantees the high accuracy compared with the prior works. Also, it shows a good dynamic performance because the mismatch is corrected continuously. It is implemented in 0.13um CMOS process and the die area is $100{\mu}m\;{\times}\;160{\mu}m$. The voltage swing is from 0.2V to 1V at supply voltage of 1.2V. The charging and discharging currents are $100{\mu}A$, respectively and the current mismatch due to the PVT variation is less than 1%.

A 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for High-Quality Video Systems (고화질 영상 시스템 응용을 위한 12비트 130MS/s 108mW $1.8mm^2$ 0.18um CMOS A/D 변환기)

  • Han, Jae-Yeol;Kim, Young-Ju;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.45 no.3
    • /
    • pp.77-85
    • /
    • 2008
  • This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

A 12b 1kS/s 65uA 0.35um CMOS Algorithmic ADC for Sensor Interface in Ubiquitous Environments (유비쿼터스 환경에서의 센서 인터페이스를 위한 12비트 1kS/s 65uA 0.35um CMOS 알고리즈믹 A/D 변환기)

  • Lee, Myung-Hwan;Kim, Yong-Woo;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.45 no.3
    • /
    • pp.69-76
    • /
    • 2008
  • This work proposes a 12b 1kS/s 65uA 0.35um CMOS algorithmic ADC for sensor interface applications such as accelerometers and gyro sensors requiring high resolution, ultra-low power, and small size simultaneously. The proposed ADC is based on an algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. Two versions of ADCs are fabricated with a conventional open-loop sampling scheme and a closed-loop sampling scheme to investigate the effects of offset and 1/f noise during dynamic operation. Switched bias power-reduction techniques and bias circuit sharing reduce the power consumption of amplifiers in the SHA and MDAC. The current and voltage references are implemented on chip with optional of-chip voltage references for low-power SoC applications. The prototype ADC in a 0.35um 2P4M CMOS technology demonstrates a measured DNL and INL within 0.78LSB and 2.24LSB, and shows a maximum SNDR and SFDR of 60dB and 70dB in versionl, and 63dB and 75dB in version2 at 1kS/s. The versionl and version2 ADCs with an active die area of $0.78mm^2$ and $0.81mm^2$ consume 0.163mW and 0.176mW at 1kS/s and 2.5V, respectively.

Discharge Rate Prediction of a new Sandbypassing System in a Field (새로운 샌드바이패싱 시스템의 토출율 예측을 위한 현장실험 연구)

  • Kweon, Hyuck-Min;Park, Sang-Shin;Kwon, Oh-Kyun
    • Journal of Korean Society of Coastal and Ocean Engineers
    • /
    • v.23 no.4
    • /
    • pp.292-303
    • /
    • 2011
  • A new type of sand bypassing system is proposed for recovering the eroded beach in this study. This system provides an added methodology to the soft defence which is main recovery method for the coastal shore protection in the world. The study proposes a conceptional design and manufacturing procedure for the relatively small size machine of sand bypassing. In order to get the discharging volume information, the power capacity of the system is tested in the field. The discharge rate of the new system shows up to the expected maximum of 618 ton/hr which is 9.6% lower than that by theoretical calculation. It gives a resonable agreement in this system when the flow is assumed to be of the high density. In this study, the delivering volume of sand is estimated according to the discharge rate. The combination of 300 mm(12 inch) intake and 250 mm(10 inch) discharge pipe line has the pumping capacity of $103\;m^3/hr$ which is nearly the same as that of South Lake Worth Inlet sand bypassing system, Florida, U.S.A.. The proposed system added the mobility to its merit. The unit price of Florida's sand bypassing is $$8~9/m^3$ (US). The system would be economically suitable for small volume of sand because no additional equipment is necessary for the intake. The diesel fuel of 25~30 l/hr was consumed during the system operation. The multiple working system would be the next investigation target for large volume of sand.

The Design of A Fast Two′s Complement Adder with Redundant Binary Arithmetic (RB 연산을 이용한 고속 2의 보수 덧셈기의 설계)

  • Lee, Tae-Uk;Jo, Sang-Bok
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.37 no.5
    • /
    • pp.55-65
    • /
    • 2000
  • In this paper a new architecture of 24-bit two's complement adder is designed by using RB(Redundant Binary) arithmetic which has the advantage of CPF(Carry-Propagation-Free). A MPPL(Modified PPL) XOR/XNOR gate is applied to improve a TC2RB(Two's Complement to RB SUM converter) speed and to reduce the number of transistors, and we proposed two types adder which used a fast RB2TC(RB SUM to Two's Complement converter). The property of two types adder is followings. The improvement of TYPE 1 adder speed is archived through the use of VGS(Variable Group Select) method and TYPE 2 adder is through the use of a 64-bit GCG(Group Change bit Generator) circuit and a 8-bit TYPE 1 adder. For 64-bit, TYPE 1 adder can be expected speed improvement of 23.5%, 25.7% comparing with the CLA and CSA, and TYPE 2 adder can be expected 41.2%, 45.9% respectively. The propagation delay of designed 24-bit TYPE 1 adder is 1.4ns and TYPE 2 adder is 1.2ns. The implementation is highly regular with repeated modules and is very well suited for microprocessor systems and fast DSP units.

  • PDF