• 전자공학회논문지 IE
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• v.47 no.4
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• pp.18-27
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• 2010

This paper is designed the efficient Data Acquisition System for an vibration of rotatory machines. The Data Acquisition System is consist of the analog logic having signal filer and amplifier, and digital logic with ADC, DSP, FPGA and FIFO memory. The vibration signal of rotatory machines acquired from sensors is controlled by the FPGA device through the analog logic and is saved to FIFO memory being converted analog to digital signal. The digital signal process is performed by the DSP using the vibration data in FIFO memory. The vibration factor of the rotatory machinery analysis and diagnosis is defined the RMS, Peak to Peak, average, GAP, FFT of vibration data and digital filtering by DSP, and is need to follow as being happened the event of vibration and make an application to an warning system. It takes time to process the several analysis step of all vibration data and the event follow, also special event. It should be continuously performed the data acquisition and the process, however during processing the input signal the DSP can not be performed to the acquisited data after then, also it will be lose the data at several channel. Therefore it is that the system uses efficiently the DSP and FPGA devices for reducing the data lose, it design to process a part of the signal data to FPGA from DSP in order to minimize the process time, and a process to parallel process system, as a result of design system it propose to method of faster process and more efficient data acquisition system by using DSP and FPGA than signal DSP system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.60-67
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• 2008

A low-power 2.4GHz fractional-N frequency synthesizer has been designed for 2.4GHz ISM band applications such as Bluetooth, Zigbee, and WLAN. To achieve low-power characteristic, the design has been focused on the power optimization of power-hungry blocks such as VCO, prescaler, and ${\Sigma}-{\Delta}$ modulator. An NP-core type VCO is adopted to optimize both phase noise and power consumption. Dynamic D-F/Fs with no static DC current are employed in designing the low-power prescaler circuit. The ${\Sigma}-{\Delta}$ modulator is designed using a modulus mapping circuit for reducing hardware complexity and power consumption. The designed frequency synthesizer which was fabricated using a $0.18{\mu}m$ CMOS process consumes 7.9mA from a single 1.8V supply voltage. The experimental results show that a phase noise of -118dBc/Hz at 1MHz offset, the reference spur of -70dBc at 25MHz offset, and the channel switching time of $15{\mu}s$ over 25MHz transition have been achieved. The designed chip occupies an area of $1.16mm^2$ including pads where the core area is only $0.64mm^2$.

• Journal of Applied Tourism Food and Beverage Management and Research
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• v.8
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• pp.123-144
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• 1997

This study, by setting the systems of room sale promotion, analyzing the actual status and the present working state with its center on the 'RHotel' that is a special grade-two hotel and the sales promotion activities of each type, intends to understand the presentstatus of the hotel and present its problems and the method for improvement. The strategy of salespromotion and the ineffectivenessof the system organization were found to be imminent in the sales promotion activities as its problems, and the importanceis being not attached to the actual substance rather than to the actualresults, such as the advertisement and publicity strategies, the irrationality of sales personnel controland its evaluation method, and therefore, the goal-oriented control is not being takenad its problems are emerging. Therefore, as an improvement plan, we ought to put the plan of the hotel merchandising into action for customers to buy what they want, the establishment of the customer-oriented sales promotionservice and the communication channel using the brand-new managerial skills, systemaizesales promotion method sand strategies, develop the organizational and systematic strategies develop the organizatinal and systemactic strategies and goods for the sake of the image-making and room sales promotion of hotels, develop the activation ways of flexible operation, and also need to develop the skills of sales promotion. Accordingly, by doing irrationalsales activities in the system and the promotion with its center on the sales promotion department, and it sis urgently required that we streng then the comodity developments fitting the hotel's traits, such as uniformpolicy of cost, mass-communicationactivities for sales promotion, the improvement of non-effectiveness, and advertisement of hotel items, and the publishing of public relation books. Therefore, the best weapon for hotels before other purchaseis to be discriminatized from other competitive hotel with theunderstanding of the psychology and activities of customers, and the communicatin with customers, and to set up organicprograms of sales promotionstrategies. Also we must promote our sales in accordance with the desire of new customers, gater the market information of customers, all the time, and systematize the facility improvement, managerial policy, business strategiescorresponding with the desire of customers. By doing so, we are able to seek, at the same time, both the satis faction of customers and the sales maximization of the hotels that will perfrom the activities of sales promotion and management.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.1
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• pp.48-61
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• 1989

In this paper, two-dimensional numerical simulation of GaAs MESFFT with 0.7${\mu}m$ gate length is perfomed. Drift-diffusion model which consider that mobility is a function of local electric field, is used. As a discretization method, instead of FDM (finite difference method) and FEM (finite element method), the Control-Volume Formulation (CVF) is used and as a numerical scheme current hybrid scheme or upwind scheme is replaced by power-law scheme which is very approximate to exponential scheme. In the process of numerical analysis, Peclet number which represents the velocity ratio of drift and diffusion, is introduced. And using this concept a current equation which consider numerical scheme at the interface of control volume, is proposed. The I-V characteristics using the model and numerical method has a good agreement with that of previous paper by others. Therefore, it is confined that it may be useful as a simulator for GaAs MESFET. Besides I-V characteristics, the mechanism of both velocity saturation in drift-diffusion model is described from the view of velocity and electric field distribution at the bottom of the channel. In addition, the relationship between the mechanism and position of dipole and drain current, are described.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.355-355
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• 2002

In this paper, we designed a FPU(floating point unit) that it is very important and requires of high density when digital audio is designed. Almost audio system must support the multi-channel and required for high quality. A floating point arithmetic function in MPEG-2 AAC that implemented by hardware is able to realtime decoding when DSP realization. The reason is that MPEG-2 AAC is compatible to the Audio field of MPEG-4 and afterwards. We designed a FPU by hardware to increase the speed of a floating point unit with much calculation part in the MPEG-2 AAC Decoder. A FPU is composed of a multiplier and an adder. A multiplier used the Radix-4 Booth algorithm and an adder adopted 1's complement method for speed up. A form of a floating point unit has 8bit of exponent part and 24bit of mantissa. It's compatible with the IEEE single precision format and adopted a pipeline architecture to increase the speed of a processor. All of sub blocks are based on ISO/IEC 13818-7 standard. The algorithm is tested by C language and the design does by use of VHDL(VHSIC Hardware Description Language). The maximum operation speed is 23.2MHz and the stable operation speed is 19MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.1-7
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• 2006

3-dimensional(3-D) simulations of ideal double-gate bulk FinFET were performed extensively and the electrical characteristics. were analyzed. In 3-D device simulation, we changed gate length($L_g$), height($H_g$), and channel doping concentration($N_b$) to see the behaviors of the threshold voltage($V_{th}$), DIBL(drain induced barrier lowering), and SS(subthreshold swing) with source/drain junction depth($X_{jSDE}$). When the $H_g$ is changed from 30 nm to 45nm, the variation gives a little change in $V_{th}$(less than 20 mV). The DIBL and SS were degraded rapidly as the $X_{jSDE}$ is deeper than $H_g$ at low fin body doping($1{\times}10^{16}cm^{-3}{\sim}1{\times}10^{17}cm^{-3}$). By adopting local doping at ${\sim}10nm$ under the $H_g$, the degradation could be suppressed significantly. The local doping also alleviated $V_{th}$ lowering by the shallower $X_{jSDE}\;than\;H_g$ at low fin body doping.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.1
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• pp.77-82
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• 2017

This paper related with the VSS_SE-MMA (Varying Step Size_Signed Error-MMA) which possible to improving the equalization performance that employing the varying adaptive step size based on the nonlinearities of error signal of SE-MMA (Signed Error-MMA), compensates the intersymbol interference by distortion occurs at the communication channel, in the transmitting the spectral efficient nonconstant modulus signal such as 16-QAM. The SE-MMA appeared to the reducing the computational arithematic operation using the polarity of error signal in the updating the tap coefficient of present MMA adaptive equalizer, but have a problem of equalization performance degradation. The VSS_SE-MMA improves the problem of such SE-MMA, using the varying step size consider the error signal in the update the adaptive equalizer tap coefficient, and its improved performance were confirmed by simulation. For this, the output signal constellation of equalizer, the residual isi and maximum distortion, MSE and SER were applied. As a result of computer simulation, it was confirmed that the VSS_SE-MMA algorithm has nearly same in convergence speed and has more good performance in every performance index at the steady state.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.3 s.345
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• pp.39-48
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• 2006

In this paper, we analyze the spectral efficiency of multicarrier-code division multiple access (MC-CDMA) scheme. First, we derive a generalized formula for the spectral efficiency according to the number of subcarriers involved in, code division multiplexing and the number of codes used (i.e., loading factor), under a given set of channel coefficients. Also, we derive a generalized formula for spectral efficiency of various reduced-complexity systems that divide the full sets of subcarriers into several groups of subcarriers for code division multiplexing. Then, through these derivations, we establish an inter-relationship between the frequency selectivity and diversity order according to the number of multipaths. From the results, we choose the smallest code length while maximizing the diversity effect, provide an optimum subcarrier allocation strategy, and finally suggest a system structure for capacity-maximizing under the smallest code length. Through numerical analyses under simulated environments, we analyze the properties of spectral efficiency of various systems with reduced complexity and choose a major contributing factors to system design and a better system design methodology. Finally, we compare the spectral efficiency of the MC-CDMA scheme and orthogonal frequency division multiplexing (OFDM) scheme to make a relationship between both schemes.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.397-409
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• 2003

This paper describes an implementation of radix-4 trellis parallel architecture and backward state transition control trace back Viterbi decoder, and presents the application results to high speed wireless LAN. The radix-4 parallelized architecture Vietrbi decoder can not only improve the throughput with simple structure, but also have small processing delay time and overhead circuit compared to M-step trellis architecture one. Based on these features, this paper addresses a novel Viterbi decoder which is composed of branch metric computation, architecture of ACS and trace back decoding by sequential control of backward state transition for the implementation of radix-4 trellis parallelized structure. With the proposed architecture, the decoding of variable code rate due to puncturing the base code can easily be implemented by the unified Viterbi decoder. Moreover, any additional circuit and/or peripheral control logic are not required in the proposed decoder architecture. The trace back decoding scheme with backward state transition control can carry out the sequential decoding according to ACS cycle clock without additional circuit for survivor memory control. In order to evaluate the usefulness, the proposed method is applied to channel CODEC of the IEEE 802.11a high speed wireless LAN, and HDL coding simulation results are presented.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.3
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• pp.22-30
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• 2010

This paper proposes a combination system of Adaptive Modulation and Coding (AMC) and Multiple Input Multiple Output (MIMO), which improves the throughput and has a better reliability. In addition, the system includes Precoding, Antenna Subset Selection and MIMO Mode Selection scheme. Finally, we make a performance analysis of the proposed system. The principal environmental parameters for the simulation experiment consist of a frequency non-selective rayleigh fading channel and a Spreading Factor (SF) of 16. Other parameters may be included in order to fulfill the requirements of the HSDP A Standard. The proposed system has a higher throughput and more reliability than the conventional system, which does not include MIMO Mode Selection scheme, Precoding or Antenna Subset Selection. According to the simulation results, the proposed system reaches the maximum throughput at 8dB, presentlng an improvement of 6dB and twice higher throughput, respect to the conventional system. Specifically, at the point of -6dB, the conventional system reaches 2.5Mbps, while the proposed system reaches 6.4Mbps at the same SNR. Also, at the point of 2dB, each system reaches 7.5Mbps (conventional system) and 15.3Mbps (proposed system), with near twice the difference. According to the results exposed above, we can conclude that the system proposed in this paper has, as the greatest contribution, the improvement of the throughput, especially, the average throughput.