• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.27 no.8
• /
• pp.717-724
• /
• 2016

This paper presents design of a 40 GHz CMOS PLL frequency synthesizer for a 60 GHz sliding-IF RF transceiver. For stable locking over a wide bandwith for a injection-locked frequency divider, an inductive-peaking technique is employed so that it ensures the PLL can safely lock across the very wide tuning range of the VCO. Also, Injection-locked type LC-buffer with low-phase noise and low-power consumption is added in between the VCO and ILFD so that it can block any undesirable interaction and performance degradation between VCO and ILFD. The PLL is designed in 65 nm CMOS precess. It covers from 37.9 to 45.3 GHz of the output frequency. and its power consumption is 74 mA from 1.2 V power supply.

• Journal of Advanced Navigation Technology
• /
• v.16 no.5
• /
• pp.810-816
• /
• 2012

In this paper, BER(Bit Error Ratio) performances of the TransferJet system, which is the standard of a close proximity inductive wireless communication system, are presented and analyzed. Comparing to other wireless communication systems, the TransferJet system has some advantages such as short communication range(i.e., high security in the wireless communication environments), fewer effects of multipath distortion, and higher transmission rate. In order to demodulate the received signal, either SC(Soft-decision Combining) or HC(Hard-decision Combining) can apply to the despreader and demodulator of the receiver. When the spreading factor is more than 4, the SC scheme approximately has a minimum signal-to-noise ratio gain of 2 dB over the HC scheme. Moreover, from simulation results, we can conclude that the quantization bits of 3 bits are an optimum value for the SC scheme in the TransferJet system since the 3-bit quantization achieves nearly the performance as that attained by double-precision floating-point.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.4 s.346
• /
• pp.16-22
• /
• 2006

Gigabit transimpedance amplifiers are realihzed in submicron CMOS technologies for Gigabit Ethernet applications. The regulated cascode technique is exploited to enhance the bandwidth and noise performance simultaneously so that it can isolate the large input parasitic capacitance including photodiode capacitance from the determination of the bandwidth. The 1.25Gb/s TIA implemented in a 0.6um CMOS technology shows the measured results of 58dBohm transimpedance gain, 950MHz bandwidth for a 0.5pF photodiode capacitance, 6.3pA/sqrt(Hz) average noise current spectral density, and 85mW power dissipation from a single 5V supply. In addition, a 10Gb/s TIA is realized in a 0.18um CMOS incorporating the RGC input and the inductive peaking techniques. It provides 59.4dBohm transimpedance gain, 8GHz bandwidth for a 0.25pF photodiode capacitance, 20pA/sqrt(Hz) noise current spectral density, and 14mW power consumption for a single 1.8V supply.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.1
• /
• pp.38-46
• /
• 1999

o.25${\mu}m$ T-shaped gate P-HEMT is fabricated and used for design of X0band three stage monolithic microwave integrated circuit(MMIC) low noise amplifier(LNA). The fabricated P-HEMT exhibits an extrinsis transconductance of 400mS/mm and a drain current of 400mA/mm. The RF and noise characteristics show that the current gain cut off frequency is 65GHz and minimum noise figure(NFmin) of 0.7dB with an associated gain of 14.8dB at 9GHz. In the design of the three stage LNA, we have used the inductive series feedback circuit topology with the short stub. The effects of series feedback to the noise figure, the gain, and the stability have been investigated to find the optimal short stub length. The designed three staage LNA showed a gain of above 33dB, a noise figure of under 1.2dB, and ainput/output return loss of under 15dB and 14dB, respectively. The results show that the fabricated P-HEMT is very suitable for a X-band LNA with high gain.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.1
• /
• pp.122-130
• /
• 2015

This paper presents a 6 Gb/s 4-channel arrayed transimpedance amplifiers (TIA) with the gain control for 4-channel passive optical network in $0.13{\mu}m$ complementary metal oxide semiconductor (CMOS) technology. A regulated cascode input stage and inductive-series peaking are proposed in order to increase the bandwidth. Also, a variable gain control is implemented to provide flexibility to the overall system. The TIA has a maximum $98.1dB{\Omega}$ gain and an input current noise level of about 37.8 pA/Hz. The die area of the fabricated TIA is $1.9mm{\times}2.2mm$ for 4-channel. The power dissipation is 47.64 mW/1ch.

• Journal of Electrical Engineering and Technology
• /
• v.13 no.6
• /
• pp.2335-2343
• /
• 2018

This paper proposes an optimal damping control algorithm of the DTI (Direct Two-level Inverter) to miniaturize and reduce the weight of auxiliary power supply for railway vehicles. The conventional auxiliary power supply for railway vehicles uses a DC-DC converter to maintain the inverter input power from the line voltage smoothly. The proposed topology does not use a DC-DC converter for reducing of manufacturing and maintenance costs. It also proposes a DTI topology removed damping resistors that generate ground signal noise in a certain period. At this time, a resonance phenomenon of DC-link voltage occurs due to variation of the inductive load, and a method of controlling the resonance phenomenon of DC-link voltage is required. In order to suppress the resonance phenomenon of the DC-link voltage, at a point before resonance occurs, this paper introduces an algorithm to suppress the resonance phenomenon of DC-link voltage by compensating the resonance component of the q axis voltage of the synchronous reference frame. The proposed algorithm verifies the effect through simulation and experiment.

• Proceedings of the KIEE Conference
• /
• 2005.07b
• /
• pp.1038-1040
• /
• 2005

This paper describes the optimal design, construction and performance evaluation of voltage divider used in high power testing laboratory for voltage measuring system. These dividers, which are of R, C, R&C type voltage dividers, the voltage to be measured range from voltage to several ten kilovolts, the frequency of the signals has a bandwidth from DC to megaHertz Measuring transient voltage and currents in the high voltage power laboratory is generally accompanied by electromagnetic interface and induced noise. above all, the measuring capabilities of voltage measuring system are dependent upon short response time and it must be as free as possible of inductive effects. In this paper presents both characteristic of voltage divider and design of voltage measuring system.

• Journal of Korean Society of Industrial and Systems Engineering
• /
• v.19 no.39
• /
• pp.47-61
• /
• 1996

We propose a parallel neural network model in which patterns are clustered and patterns in a cluster are studied in a parallel neural network. The learning algorithm used in this paper is based on LVQ algorithm of Kohonen(1990) for clustering and ADALINE(Adaptive Linear Neuron) network of Widrow and Hoff(1990) for parallel learning. The proposed algorithm consists of two parts. First, N patterns to be learned are categorized into C clusters by LVQ clustering algorithm. Second, C patterns that was selected from each cluster of C are learned as input pattern of ADALINE(Adaptive Linear Neuron). Data used in this paper consists of 250 patterns of ASCII characters normalized into $8\times16$ and 1124. The proposed algorithm consists of two parts. First, N patterns to be learned are categorized into C clusters by LVQ clustering algorithm. Second, C patterns that was selected from each cluster of C are learned as input pattern of ADALINE(Adaptive Linear Neuron). Data used in this paper consists 250 patterns of ASCII characters normalized into $8\times16$ and 1124 samples acquired from signals generated from 9 car models that passed Inductive Loop Detector(ILD) at 10 points. In ASCII character experiment, 191(179) out of 250 patterns are recognized with 3%(5%) noise and with 1124 car model data. 807 car models were recognized showing 71.8% recognition ratio. This result is 10.2% improvement over backpropagation algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.8 s.338
• /
• pp.53-60
• /
• 2005

Recently, sub-micron CMOS technologies have taken the place of III-V materials in a number of areas in integrated circuit designs, in particular even for the applications of gjgabit optical communication applications due to its low cost, high integration level, low power dissipation, and short turn-around time characteristics. In this paper, a four-channel transimpedance amplifier (TIA) array is realized in a standard 0.35mm CMOS technology Each channel includes an optical PIN photodiode and a TIA incorporating the fully differential regulated cascode (RGC) input configuration to achieve effectively enhanced transconductance(gm) and also exploiting the inductive peaking technique to extend the bandwidth. Post-layout simulations show that each TIA demonstrates the mid-band transimpedance gain of 59.3dBW, the -3dB bandwidth of 2.45GHz for 0.5pF photodiode capacitance, and the average noise current spectral density of 18.4pA/sqrt(Hz). The TIA array dissipates 92mw p in total from a single 3.3V supply The four-channel RGC TIA array is suitable for low-power, high-speed optical interconnect applications.