• 전자공학회논문지
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• 제49권9호
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• pp.259-269
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• 2012

전원 전압이 낮아지고, 칩의 동작 속도가 빨라짐에 따라 온-칩 인덕턴스를 포함한 power distribution network (PDN) 분석이 중요해 질 것으로 예측된다. 본 논문에서는 일반적인 온-칩 전력 격자 구조에 적용시킬 수 있는 효과적인 인덕턴스 추출방법에 대해 제안한다. Chip layout에 적용할 수 있는 loop 인덕턴스 모델을 제시하고, 그 모델을 사용하여 post layout RC extraction netlist로 부터 인덕턴스를 포함한 netlist를 추출할 수 있는 tool을 개발하였다. 제안된 loop 인덕턴스 모델과 개발된 tool의 정확성은 회로 simulation을 통해 PEEC 모델과 비교하여 검증하였다. 인덕턴스 추출 방법을 실제 chip layout에 적용시켜 on-chip inductance를 포함한 PDN의 voltage fluctuation을 예측하였다. 패키지와 PCB 모델을 포함한 co-simulation 모델을 구성하여 on-chip inductance의 영향을 분석하였다.

• 한국전자파학회논문지
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• 제14권8호
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• pp.823-829
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• 2003

고주파용 마이크로스트립 선로의 모델링에 필수적인 인덕턴스의 빠른 추출을 위해서 고속화 알고리즘(fast mutilpole method)과 결합된 적응 PEEC 격자분할법(adaptive PEEC grid refinement algorithm)을 제안하였다. 격자의 세분화는 마이크로스트립 선로의 구조와 사용주파수에 따른 전류분포에 적합하도록 이루어졌는데, 이 적응 격자는 주로 전류분포가 높은 영역에서 더 세분화된다. 이 기법을 이용하여 마이크로스트립 선로의 인덕턴스를 구하였고, 계산결과는 빠르게 수렴하여 계산시간과 격자 수를 줄이는데 효율적임을 보였다.

• Journal of Power Electronics
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• 제19권1호
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• pp.307-315
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• 2019

Condition monitoring has been recognized as an effective and low-cost method to enhance the reliability and improve the maintainability of power electronic converters. In power electronic converters, high-frequency oscillation occurs during the switching transients of power transistors, which is known as ringing. The ringing frequency mainly depends on the values of the parasitic capacitance and stray inductance in the oscillation loop. Although circuit stray inductance is an important factor that leads to the ringing, it does not change with transistor aging. A shift in either the inside inductance or junction capacitance is an important failure precursor for power transistors. Therefore, ringing frequency can be used to monitor the health of power transistors. However, the switching actions of power transistors usually result in a dynamic behavior that can generate oscillation signals mixed with background noise, which makes it hard to directly extract the ringing frequency. A frequency extraction method based on empirical mode decomposition (EMD) and Fast Fourier transformation (FFT) is proposed in this paper. The proposed method is simple and has a high precision. Simulation results are given to verify the ringing analysis and experimental results are given to verify the effectiveness of the proposed method.

• ETRI Journal
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• 제43권5호
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• pp.891-899
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• 2021

We propose a stray inductance extraction method on power modules of the few-kilovolts/several-hundred-amperes class using only low voltages and low currents. The method incorporates a double-pulse generator, a level shifter, a switching device, and a load inductor. The conventional approach generally requires a high voltage of more than half the power module's rated voltage and a high current of around half the rated current. In contrast, the proposed method requires a low voltage and low current environment regardless of the power module's rated voltage because the module is measured in a turn-off state. Both theoretical and experimental results are provided. A physical circuit board was fabricated, and the method was applied to three commercial power modules with EconoDUAL3 cases. The obtained stray inductance values differed from the manufacturer-provided values by less than 1.65 nH, thus demonstrating the method's accuracy. The greatest advantage of the proposed approach is that high voltages or high currents are not required.

• ETRI Journal
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• 제28권1호
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• pp.115-118
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• 2006

In this letter, a simple model parameter extraction methodology for an on-chip spiral inductor is proposed based on a wide-band inductor model that incorporates parallel inductance and resistance to model skin and proximity effects, and capacitance to model the decrease in series resistance above the frequency near the peak quality factor. The wide-band inductor model does not require any frequency dependent elements, and model parameters can be extracted directly from the measured data with some curve fitting. The validity of the proposed model and parameter extraction methodology are verified with various size inductors fabricated using $0.18\;{\mu}m$ CMOS technology.

• 전자공학회논문지A
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• 제31A권10호
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• pp.94-100
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• 1994

By using the RAPHAEL 3D inductance calculation program RI3, the PGA package inductance values of INTEL i486 microprocessor have been extracted. The lead frame layouts are drawn using the mentor Boardstation and the output files are converted into the RI3 program input format of RAPHAEL. The power and ground planes of the PGA package are modeled y grid-line structures of single bars. The capacitance valuse of signal lines have been clalculated by using the RAPHAEL 2D/3D capacitance extraction program. The extraced L, C, R values have been converted into the SPICE netlist formats with lumped circuit model for future use in the signal ingegrity analysis.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.871-874
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• 1998

A new transmission line parameter extraction method of iC interconnects on silicon substrate is presented. To extract the acurate parameters, the silicon substrate effects were taken into account. Since the electromagnetic fields under the silicon substrate are propagated with slow wave mode, effective dielectric constant and different ground plane with the multi-layer dielectric structures were employed for inductance and capacitance matrix determination. Then accurate signal transients simulation were performed with HSPICE by using the parameters. It was shown that the simulation resutls has an excellent agreement with TDR/TDT measurements.

• 전기학회논문지
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• 제57권3호
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• pp.446-452
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• 2008

To design a spiral inductor a genetic algorithm is applied with fast computing technique. For the inductance extraction of the given geometry the fast multipole method is used, also the distributed computing technique using 10 personal computers is introduced for the massive computation of the genetic algorithm. A few important design parameters are used as genes for the optimization in the genetic algorithm. The target function is chosen as mean square error of the inductance at several sampling frequency points. A large-scaled inductor is fabricated and compared with the simulated data.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.645-648
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• 1998

We used a three-dimensional inductance extraction program, Fasthenry for optimal design of the spiral inductors on silicon substrate. The inductance and quality factor of the spiral inductors with various design parameters were calculated so that the optimal parameter value was determined. The spiral inductors then were fabricated using different foundary processes and were measured using the network analyzer and microwave probes. The pad and other parasitics of measurement system were de-embedded using the y-parameter calibration technique. the inductors fabricated using the LG 0.8um process and HP 0.5um process showed the quality factor of 5.8 and 3, respectively. Finally the equivalent circuit farameters of the spiral inductors on silicon substrate were extracted from the measurement data using the matlab.

• 한국전자파학회논문지
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• 제7권5호
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• pp.395-407
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• 1996

In this paper, we describe the crossover of the parasitic capacitance at the interconnections for the system miniature, analyse ground capacitance and mutual capacitance due to actually coupled line in the ICs or MCMs. From the results of deviding interconnection line with infinite parts, using Green's function with image charge method and moments, we could obtain 70% decrease of system runtime parasitic inductance because of simplicity of transforming formular.