• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.14-19
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• 2011

We have fabricated GaN Schottky barrier diode (SBD) for high-voltage applications on Si substrate. The leakage current and the electrical characteristics of GaN SBD are investigated by annealing metal-semiconductor junctions. Ohmic junctions of Ti/Al/Mo/Au and Schottky junctions of Ni/Au are used in the fabrication. A test structure is proposed to measured buffer leakage current through a mesa structure. When annealing temperature is increased from $700^{\circ}C$ to $800^{\circ}C$, measured buffer leakage current is also increased from 87 nA to 780 nA at the width of 100 ${\mu}m$. The diffusion of Au, Ti, Mo, O into GaN buffer layer increases the leakage current and that is verified by Auger electron spectroscopy. Experimental results show that the low leakage current and the high breakdown voltage of GaN SBD are achieved by annealing metal-semiconductor junctions.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.1
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• pp.75-83
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• 2008

We propose a welfare interface using multiple fecial features tracking, which can efficiently implement various mouse operations. The proposed system consist of five modules: face detection, eye detection, mouth detection, facial feature tracking, and mouse control. The facial region is first obtained using skin-color model and connected-component analysis(CCs). Thereafter the eye regions are localized using neutral network(NN)-based texture classifier that discriminates the facial region into eye class and non-eye class, and then mouth region is localized using edge detector. Once eye and mouth regions are localized they are continuously and correctly tracking by mean-shift algorithm and template matching, respectively. Based on the tracking results, mouse operations such as movement or click are implemented. To assess the validity of the proposed system, it was applied to the interface system for web browser and was tested on a group of 25 users. The results show that our system have the accuracy of 99% and process more than 21 frame/sec on PC for the $320{\times}240$ size input image, as such it can supply a user-friendly and convenient access to a computer in real-time operation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.10-17
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• 2007

It opens a new horizon on spintronics for the potential application of MTJ as a universal logic element, to employ the magneto-logic in substitution for the transistor-based logic device. The magneto-logic based on the MTJ element shows many potential advantages, such as high density, and nonvolatility. Moreover, the MTJ element has programmability and can therefore realize the full logic functions just by changing the input signals. This magneto-logic using MTJ elements can embody the reconfigurable circuit to overcome the rigid architecture. The established magneto-logic element has been designed and fabricated on a triple-layer MTJ. We present a novel magneto-logic structure that consists of a single layer MTJ and a current driver, which requires less processing steps with enhanced functional flexibility and uniformity. A 4-bit gray counter is designed to verify the magneto-logic functionality of the proposed single-layer MTJ and the simulation results are presented with the HSPICE macro-model of MTJ that we have developed.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.5
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• pp.95-101
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• 2008

Modeling of stock prices forecast has been considered as one of the most difficult problem to develop accurately since stock prices are highly correlated with various environmental conditions including economics and political situation. In this paper, we propose a agent system approach to predict Korea Composite Stock Price Index (KOSPI) using neural network and statistical methods. To minimize mean of prediction error and variation of prediction error, agent system includes sub-agent modules for feature extraction, variables selection, forecast engine selection, and forecasting results analysis. As a first step to develop agent system for KOSPI forecasting, twelve economic indices are selected from twenty two basic standard economic indices using principal component analysis. From selected twelve economic indices, prediction model input variables are chosen again using best-subsets regression method. Two different types data are tested for KOSPI forecasting and the Prediction results showed 11.92 points of root mean squared error for consecutive thirty days of prediction. Also, it is shown that proposed agent system approach for KOSPI forecast is effective since required types and numbers of prediction variables are time-varying, so adaptable selection of modeling inputs and prediction engine are essential for reliable and accurate forecast model.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.6
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• pp.34-51
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• 2008

Today, the Internet is a part of our life. For that reason, we regard revealing characteristics of Internet traffic as an important research theme. However, Internet traffic cannot be easily manipulated because it usually occupy huge capacity. This problem is a serious obstacle to analyze Internet traffic. Many researchers use various sampling techniques to reduce capacity of Internet traffic. In this paper, we compare several famous sampling techniques, and propose efficient sampling scheme. We chose some sampling techniques such as Systematic Sampling, Simple Random Sampling and Stratified Sampling with some sampling intensities such as 1/10, 1/100 and 1/1000. Our observation focused on Traffic Volume, Entropy Analysis and Packet Size Analysis. Both the simple random sampling and the count-based systematic sampling is proper to general case. On the other hand, time-based systematic sampling exhibits relatively bad results. The stratified sampling on Transport Layer Protocols, e.g.. TCP, UDP and so on, shows superior results. Our analysis results suggest that efficient sampling techniques satisfactorily maintain variation of traffic stream according to time change. The entropy analysis endures various sampling techniques well and fits detecting anomalous traffic. We found that a traffic volume diminishment caused by bottleneck could induce wrong results on the entropy analysis. We discovered that Packet Size Distribution perfectly tolerate any packet sampling techniques and intensities.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.26-36
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• 2014

The needs of active phased arrays antenna system is getting more increased for IMT-Advanced system efficiency. The active phased array structure consists of lots of small transceivers and radiation elements to increase system efficiency. The minimized module of high efficiency transceiver is key for system implementation. The power amplifier of transmitter decides efficiency of base-station. In this paper, we design and implement minimized module of high efficiency transceiver for IMT-Advanced active phased array system. The temperature compensation circuit of transceiver reduces gain error and the analog pre-distorter of linearizer reduces implemented size. For minimal size and high efficiency, the implented power amplifier consist of GaN MMIC Doherty structure. The size of implemented module is $40mm{\times}90mm{\times}50mm$ and output power is 47.65 dBm at LTE band 7. The efficiency of power amplifier is 40.7% efficiency and ACLR compensation of linearizer is above 12dB at operating power level, 37dBm. The noise figure of transceiver is under 1.28 dB and amplitude error and phase error on 6 bit control is 0.38 dB and 2.77 degree respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.94-100
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• 2014

In this paper, a design of low power Current-Reuse Voltage Controlled Oscillator (VCO) which has wide tuning range about 1.95 GHz ~ 3.15 GHz is presented. Class-C type is applied to improve phase noise and 2-Step Auto Amplitude Calibration (AAC) is used for minimizing the imbalance of differential VCO output voltage which is main issue of Current-Reuse VCO. The mismatch of differential VCO output voltage is presented about 1.5mV ~ 4.5mV. This mismatch is within 0.6 % compared with VCO output voltage. Proposed Current-Reuse VCO is designed using CMOS $0.13{\mu}m$ process. Supply voltage is 1.2 V and current consumption is 2.6 mA at center frequency. The phase noise is -116.267 dBc/Hz at 2.3GHz VCO frequency at 1MHz offset. The layout size is $720{\times}580{\mu}m^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.92-98
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• 2017

Generally, image contains geometrical and radiometric errors. Census transform can solve the stereo mismatching problem caused by the radiometric distortion. Since the general census transform compares center of window pixel value with neighbor pixel value, it is hard to obtain an accurate matching result when the difference of pixel value is not large. To solve that problem, we propose a census transform method that applies different 4-step weight for each pixel value difference by applying an assistance window inside the window kernel. If the current pixel value is larger than the average of assistance window pixel value, a high weight value is given. Otherwise, a low weight value is assigned to perform a differential census transform. After generating an initial disparity map using a weighted census transform and input images, the gradient information is additionally used to model a cost function for generating a final disparity map. In order to find an optimal cost value, we use guided filtering. Since the filtering is performed using the input image and the disparity image, the object boundary region can be preserved. From the experimental results, we confirm that the performance of the proposed stereo matching method is improved compare to the conventional method.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.236-244
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• 2003

In this paper, RF and IF circuits for mobile terminals which have usually been implemented using expensive BiCMOS processes are designed using CMOS circuits, and a Tx CMOS RF/IF single chip for PCS applications is designed. The designed circuit consists of an IF block including an IF PLL frequency synthesizer, an IF mixer, and a VGA and an RF block including a SSB RF mixer and a driver amplifier, and performs all transmit signal processing functions required between digital baseband and the power amplifier. The phase noise level of the designed IF PLL frequency synthesizer is -114dBc/Hz@100kHz and the lock time is less than $300{\mu}s$. It consumes 5.3mA from a 3V power supply. The conversion gain and OIP3 of the IF mixer block are 3.6dB and -11.3dBm. It consumes 5.3mA. The 3dB frequencies of the VGA are greater than 250MHz for all gain settings. The designed VGA consumes 10mA. The designed RF block exhibits a gain of 14.93dB and an OIP3 of 6.97dBm. The image and carrier suppressions are 35dBc and 31dBc, respectively. It consumes 63.4mA. The designed circuits are under fabrication using a $0.35{\mu}m$ CMOS process. The designed entire chip consumes 84mA from a 3V supply, and its area is $1.6㎜{\times}3.5㎜$.