• Proceedings of the Korean Society for Emotion and Sensibility Conference
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• 2012.05a
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• pp.83-84
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• 2012

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.410-413
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• 1988

In this paper, the real-time optical associative memory using multiple hologram which is generated with two angular multiplexed reference beams and Fourier transformed object beam in the $BaTiO_{3}$ crystal based on DFWM mechanism. When one image is recorded in the $BaTiO_{3}$ crystal, complete image can be recalled by 9 % partial input of the stored original image without any additional thresholding and optical feedback process. As an experimental result of multiple Fourier hologram which is recorded with two binary images, OHCHAS and PARKHK, we can obtain complete image recalled by 1/6 partial input of the stored image.

• Journal of Korea Multimedia Society
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• v.14 no.3
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• pp.368-377
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• 2011

This paper explains the hardware structure of SURF(Speeded Up Robust Feature) based feature point extractor and its FPGA verification result. SURF algorithm produces novel scale- and rotation-invariant feature point and descriptor which can be used for object recognition, creation of panorama image, 3D Image restoration. But the feature point extraction processing takes approximately 7,200msec for VGA-resolution in embedded environment using ARM11(667Mhz) processor and 128Mbytes DDR memory, hence its real-time operation is not guaranteed. We analyzed integral image memory access pattern which is a key component of SURF algorithm to reduce memory access and memory usage to operate in c real-time. We assure feature extraction that using a Vertex-5 FPGA gives 60frame/sec of VGA image at 100Mhz.

• Journal of IKEEE
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• v.27 no.3
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• pp.273-279
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• 2023

The use of line memory is essential for image filtering in image processing hardware. After input data is stored in line memory, filtering is performed after synchronization to use the stored data. A sync generator is used for synchronization, and in the case of a conventional sync generator, the input sync signal is delayed by one row of the input image. If a signal delayed by two rows is required, it is necessary to connect two modules. This approach increases the size of the hardware and cannot be designed efficiently. In this paper, we propose a sync generator that generates multiple types of delayed signals by adding a finite state machine. The hardware design was coded in Verilog HDL, and performance is verified by applying it to image processing hardware using field programmable gate array board.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.40-47
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• 2007

For image processing hardware, including a face detecting engine, efficient constitution of external and internal memories is a consequential point because huge memory is required to store various signal processing filters and incoming images. In this paper, we modified a face detect algerian of a general filter method for efficient hardware design. In the hardware, several memory design techniques are presented for efficient handling of image data : re-accessing avoidance with minimized internal memory usage, residing frequently accessed memory and sequence memory accessing. The hardware which can process 25 frame image data per one second with 40KB internal memory was verified by using ARM(S3C2440A) and Virtex4 FPGA and it is being fabricated as a ASIC chip using Samsung CMOS 0.18um technology.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.6
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• pp.231-237
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• 2004

Current paper introduces the multimedia functional module and related interface development for digital TV. The module is developed for displaying the image captured by digital still camera, camcorder, or PC in the digital TV. For these purposes, the module has the interface circuit for accessing five media type of memory cards. It decodes JPEG, BMP, or TIFF image date saved in the memory card and converts the image data to analog RGB signal. It also supports three types of output image size from HD(High Definition) to WXGA(Wide Extended Graphics Array) resolution. So the introduced module could be adopted in all kinds of digital TV set.

• Proceedings of the IEEK Conference
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• 2001.06d
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• pp.105-108
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• 2001

This paper proposed an efficient memory scheduling method (E$^2$M$^2$) by which the real-time image compression using 2-dimensional discrete wavelet transform(2-D DWT) is possible in an FPGA chip. In this paper, we assumed that the 2-D DWT was performed as the Mallat-tree. After the memory mapping method was proved in software, the memory controller was designed for an commercial SDRAM IC.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.4
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• pp.89-100
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• 2011

Physical memory analysis has been an issue on a field of live forensic analysis in digital forensics until now. It is very useful to make the result of analysis more reliable, because record of user behavior and data can be founded on physical memory although process is hided. But most memory analysis focuses on windows based system. Because the diversity of target system to be analyzed rises up, it is very important to analyze physical memory based on other OS, not Windows. Mac OS X, has second market share in Operating System, is operated by loading kernel image to physical memory area. In this paper, We propose a methodology for physical memory analysis on Mac OS X using symbol information in kernel image, and acquire a process information, mounted device information, kernel information, kernel extensions(eg. KEXT) and system call entry for detecting system call hooking. In additional to the methodology, we prove that physical memory analysis is very useful though experimental study.

• Smart Structures and Systems
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• v.30 no.3
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• pp.255-261
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• 2022

When no extensometer is available in a generic tensile-compression test carried out by a universal testing machine (for instance the model BIONIX from Material Testing Systems (MTS)), the test results only provide the relative displacement between the machine grips. The test does not provide any information on the local behaviour of the material. This contribution presents the potential of an application of Digital Image Correlation (DIC) toward the reconstruction of the behaviour along the specimen. In particular, the authors test a Ni-Ti shape memory alloys (SMA) specimen with emphasis on the coupling of the two measurement techniques.

• Journal of the Optical Society of Korea
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• v.20 no.5
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• pp.586-592
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• 2016

This paper proposes a luminance compensation method using optical sensors to achieve high luminance uniformity of active matrix organic light-emitting diode (AMOLED) displays. The proposed method compensates for the non-uniformity of luminance by capturing the luminance of entire pixels and extracting the characteristic parameters. Data modulation using the extracted characteristic parameters is performed to improve luminance uniformity. In addition, memory size is optimized by selecting an optimal bit depth of the extracted characteristic parameters according to the trade-off between the required memory size and luminance uniformity. To verify the proposed compensation method with the optimized memory size, a 40-inch 1920×1080 AMOLED display with a target maximum luminance of 350 cd/m² is used. The proposed compensation method considering a 4σ range of luminance reduces luminance error from ± 38.64%, ± 36.32%, and ± 43.12% to ± 2.68%, ± 2.64%, and ± 2.76% for red, green, and blue colors, respectively. The optimal bit depth of each characteristic parameter is 6-bit and the total required memory size to achieve high luminance uniformity is 74.6 Mbits.