• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.119-122
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• 2007

In this paper, we propose the method of hardware-design for the division operation of image frame-unit processing in mobile phone camera. Generally, there are two types of the data processing, which are the parallel and serial type. The parallel type makes it possible to process in realtime, but it needs significant hardware size due to many comparators and buffer memories. Compare the serial type with the parallel type, the hardware size of the serial type is smaller than the other because it uses only one comparator, but serial type is not able to process in realtime. To use the hardware resources efficiently, we employ the serial divider since frame-unit operation for image processing does not need realtime process. When compared with both in the same bit size and operating frequency, the hardware size of the serial divider is approximately in the ratio of 13 percentage compared with the parallel divider.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.38-45
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• 2007

A new 8-bit single-slope ADC using analog RAMP generator with digitally controllable dynamic range has been proposed and simulated for column level or per-pixel CMOS image sensor application. The conversion gain of ADC can he controlled easily by using frequency divider with digitally controllable diviber ratio, coarse/fine RAMP with class-AB op-amp, resistor strings, decoder, comparator, and etc. The chip area and power consumption can be decreased by simplified analog circuits and passive components. Proposed frequency divider has been implemented and verified with 0.65um, 2-poly, 2-metal standard CMOS process. And the functional verification has been simulated and accomplished in a 0.35$\mu$m standard CMOS process.

• Journal of the Semiconductor & Display Technology
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• v.6 no.2 s.19
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• pp.49-52
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• 2007

Characteristics of an active pixel switch readout circuit were studied by SPICE simulation. A simple readout circuit consists of an operation amplifier, a diode, and a down-counter was suggested, and its successful operation was verified by showing that the differences in the detected signal intensity are accordingly converted to modulation of the voltage pulses generated by the comparator. A scheme to use these pulses to generate the original image was also put forward.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.3
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• pp.873-879
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• 2010

In this paper, MPEG2(Moving Picture Expert Group 2) image data video decoding technique is presented, it is Huffman decoding method and fractal image method which is very complexive algorithm and have too much times to implement this method. This have defect of overlap decoding and transport work because of impossible to represent objective value of resemblance. The proposed method was calculated the mathematical absolute image resemblance and simplify the moving picture process to reducing the step of moving picture codefying. The results show that smoothed moving picture compared recent methods.

• Journal of Sensor Science and Technology
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• v.30 no.1
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• pp.61-65
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• 2021

In this study, we propose a 2500 frame per second (fps) high-speed binary complementary metal oxide semiconductor (CMOS) image sensor using a gate/body-tied (GBT) p-channel metal oxide semiconductor field effect transistor-type high-speed photodetector. The GBT photodetector generates a photocurrent that is several hundred times larger than that of a conventional N+/P-substrate photodetector. By implementing an additional binary operation for the GBT photodetector with such high-sensitivity characteristics, a high-speed operation of approximately 2500 fps was confirmed through the output image. The circuit for binary operation was designed with a comparator and 1-bit memory. Therefore, the proposed binary CMOS image sensor does not require an additional analog-to-digital converter (ADC). The proposed 2500 fps high-speed operation binary CMOS image sensor was fabricated and measured using standard CMOS process.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.4
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• pp.63-69
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• 2012

This paper describes novel scheme of a gray scale capacitive fingerprint image for high-accuracy capacitive sensor chip. The typical gray scale image scheme used a DAC of big size layout or charge-pump circuit of non-volatile memory with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit of charge sharing scheme is proposed, which uses DLC(down literal circuit) based on a neuron MOS(vMOS) and analog simple multiplexor. The detection circuit is designed and simulated in 3.3V, $0.35{\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, a pixel layout size can be reduced and the image resolution can be improved.

• Journal of the Korean Society of Costume
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• v.56 no.4 s.103
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• pp.160-170
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• 2006

The purpose of this study is to analyze the image of color combination in fashion design. For this study 14,121 color samples were collected from 116 fashion brands selected by the market segmentation based on the results of the previous studies. The brands have high market share and brand recognition in each segmental market. The color samples were measured by spectrophotometer and analyzed by the Munsell's H V/C and CIE $L^*a^*b^*$ value. The representative colors of each market were selected concerning the tensity in CIE $L^*a^*b^*$ color space and the distance between the color samples. h4 a result, 2,213 representative colors were chosen. These color samples composed top and bottom color combination samples by the program 'Item Comparator' that calculated the color differences$({\Delta}E^*)$. Top includes the items such as blouse, shirt, and coats, bottom includes the items such as skirt and pants. The color combination samples were divided into two groups. In one group ${\Delta}E^*$ was less than 30, and In the other group ${\Delta}E^*$ was 30 or more. For investigating the image of color combination, 480 rotor combination samples were classified. The image adjectives for the survey from preceding studies and brand dictionaries were 'classic', 'modern', 'feminine', 'casual', and 'romantic', which have highly preferred in women's wear brands. The result of the study is as follows; For 'classic' 'image, YR, and greyish tone were generally preferred. In the color combination of 'casual' image, the samples with PB color and greyish tone were preferred. For 'feminine' image, RP was preferred as a top color, R, RP, P were preferred as a bottom color. For 'casual' image, PB was preferred as a top color, PB, B were preferred as a bottom color. For 'romantic' image, RP was preferred as a top color, R, P were preferred as a bottom color. The bigger the color differences between the color combination samples were, the more remarkable the image of color combination samples was.

• Journal of IKEEE
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• v.13 no.4
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• pp.63-68
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• 2009

The power management integrated circuit(PMIC) for CCD image sensor is presented in this study. A CCD image sensor is very sensitive against temperature. The temperature, that is heat, is generally generated by the PMIC with low efficiency. Since the generated heat influences performance of CCD image sensor, it should be minimized by using a PMIC which has a high efficiency. In order to develop the PMIC with high efficiency, the input stage is designed with synchronous type step down DC-DC converter. The operating range of the converter is from 5V to 15V and the converter is controlled using PWM method. The PWM control circuit consists of a saw-tooth generator, a band-gap reference circuit, an error amplifier and a comparator circuit. The saw-tooth generator is designed with 1.2MHz oscillation frequency. The comparator is designed with the two stages OP Amp. And the error amplifier has 40dB DC gain and $77^{\circ}$ phase margin. The output of the step down converter is connected to input stage of the charge pump. The output of the charge pump is connected to input of the LDO which is the output stage of the PMIC. Finally, the PMIC, based on the PWM control circuit and the charge pump and the LDO, has output voltage of 15V, -7.5V, 3.3V and 5V. The PMIC is designed with a 0.35um process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.379-385
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• 2015

This paper proposes the hardware architecture of high performance ALF(Adaptive Loop Filter) for efficient filter coefficient estimation. In order to make the original image which has high resolution and high quality into highly compressed image effectively and also, subjective image quality into improved image, the ALF technique of HEVC performs a filtering by estimating filter coefficients using statistical characteristics of image. The proposed ALF hardware architecture is designed with a 2-step pipelined architecture for a reduction in performance cycle by analysing an operation relationship of Cholesky decomposition for the filter coefficient estimation. Also, in the operation process of the Cholesky decomposition, a square root operation is designed to reduce logic area, computation time and computation complexity by using the multiplexer, subtracter and comparator. The proposed hardware architecture is designed using Xilinx ISE 14.3 Vertex-7 XC7VCX485T FPGA device and can support 4K UHD@40fps in real time at a maximum operation frequency of 186MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.2
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• pp.322-329
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• 2007

A single pixel photon counting type image sensor which is applicable for medical diagnosis with digitally obtained image and industrial purpose has been designed with $0.18{\mu}m$ triple-well CMOS process. The designed single pixel for readout chip is able to be operated by single supply voltage to simplify digital X-ray image sensor module and a preamplifier which is consist of folded cascode CMOS operational amplifier has been designed to enlarge signal voltage(${\Delta}Vs$), the output voltage of preamplifier. And an externally tunable threshold voltage generator circuit which generates threshold voltage in the readout chip has been newly proposed against the conventional external threshold voltage supply. In addition, A dark current compensation circuit for reducing dark current noise from photo diode is proposed and 15bit LFSR(Linear Feedback Shift Resister) Counter which is able to have high counting frequency and small layout area is designed.