• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.138-138
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• 2000

Kinetic behaviors of homoepitaxial growth on Ni(110) surface was studied at the growth-temperature ranges 290~380 K with scanning tunneling microscopy. At low temperature (~290 K), deposited Ni grows layer-by-layer mode in the first several layers with one-dimensional islands but eventually (at > monolayers) forms three-dimensional islands througy the kinetic shortening of the average length of one-dimensional islands. At the intermediat temperature (~340 K), the three-dimensional islands were observed to be I) regular mesa-like structure with high aspect ratio (~1:10) at ~15 monolayer, ii) hut-like structure with low aspect ratio (~1:1.5) at ~35 monolayer, and iii) rounded mound structure at ~55 monolayers, due to the competition of kinetic and energetic terms. At the high temperature (~ 380 K), the flat surface with layer-by-layer mode was observed up to 50 monolayers. Microscopic orgins for the observations will be discussed on the basis of kinetic Monte Carlo simulations.

• Proceedings of the Korea Information Processing Society Conference
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• 2021.11a
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• pp.267-269
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• 2021

Trusted Execution Environment(TEE) is an execution environment provided by CPU hardware to gain guarantee that the execution context is as expected by the execution requester. Remote attestation of the execution context naturally arises from the concept of TEEs. Many implementations of TEEs use cryptographic remote attestation methods. Though the implementation of attestation may be simple, the implementation of verification may be very complex and heavy. By using a server delegating the verification process of attestation information, one may produce lightweight binaries that may verify peers and establish a secure channel with verified peers.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.230-239
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• 2012

In this paper, we present the radio-frequency (RF) modeling for gate-all-around (GAA) junctionless (JL) MOSFETs with 30-nm channel length. The presented non-quasi-static (NQS) model has included the gate-bias-dependent components of the source and drain (S/D) resistances. RF characteristics of GAA junctionless MOSFETs have been obtained by 3-dimensional (3D) device simulation up to 1 THz. The modeling results were verified under bias conditions of linear region (VGS = 1 V, VDS = 0.5 V) and saturation region (VGS = VDS = 1 V). Under these conditions, the root-mean-square (RMS) modeling error of $Y_{22}$-parameters was calculated to be below 2.4%, which was reduced from a previous NQS modeling error of 10.2%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.245-251
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• 2013

The effect of band-to-band tunneling (BTBT) leads to an obvious increase of the leakage current of junctionless (JL) transistors in the OFF state. In this paper, we propose an effective method to decline the influence of BTBT with the example of n-type double gate (DG) JL metal-oxide-semiconductor field-effect transistors (MOSFETs). The leakage current is restrained by changing the geometrical shape and the physical dimension of the gate of the device. The optimal design of the JL MOSFET is indicated for reducing the effect of BTBT through simulation and analysis.

• Journal of the Korean Vacuum Society
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• v.2 no.2
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• pp.161-165
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• 1993

The geometrical and electronic structure of epitaxially grown Ge on Si(100) and Si(111) surfaces has been studied by scanning tunneling microscopy. Since Ge atoms could be distinguished from Si atoms by scanning tunneling spectroscopy and voltage dependent STM images, the growth mode of the added layer could be studied. On the (100) surface with a (2${\times}$1) reconstruction, Ge overlayer grow preferentially on the B type step edges at 720K. On the (111) surface, Ge overlayer also grow on the step edges with (7${\times}$7) and (5${\times}$5) structure depending on their coverage and annealing temperature.

• Electrical & Electronic Materials
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• v.10 no.1
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• pp.8-14
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• 1997

The UV/O$_{3}$ dry cleaning has been well known in removing organic molecules. The UV/O$_{3}$ dry cleaning method was performed to clean the Si wafer surfaces and contact holes contaminated by organic molecules such as residual PR. During the cleaning process, the Si surfaces were analyzed with X-ray photoelectron spectroscopy (XPS), atomic force microscope (AFM) and ellipsometer. When the UV/O$_{3}$ dry cleaning at 200'C was performed for 3 minutes, the residual photoresist was almost removed on Si wafer surfaces, but Si surfaces were oxidized. For UV/O$_{3}$ application of contact hole cleaning, the contact string were formed using the equipment of ISRC (Inter-university Semiconductor Research Center). Before Al deposition, UV/O$_{3}$ (at 200.deg. C) dry cleaning was performed for 3 minutes. After metal annealing, the specific contact resistivity was measured. Because UV/O$_{3}$ dry cleaning removed organic contaminants in contact holes, the specific contact resistivity decreased. Each contact hole size was different, but the specific contact resistivities were all much the same. Thus, it is expected that the UV/O$_{3}$ dry cleaning method will be useful method of removal of the organic contaminants at smaller contact hole cleaning.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.5
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• pp.331-337
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• 2014

Ge is becoming an increasingly popular semiconductor material with high Si compatibility for on-chip optical interconnect technology. For a better manifestation of the meritorious material properties of Ge, its surface treatment should be performed satisfactorily before the electronic and photonic components are fabricated. Ex-situ rapid thermal annealing (RTA) processes with different gases were carried out to examine the effects of the annealing gases on the thin-film quality of Ge grown epitaxially on Si substrates. The Ge-on-Si samples were prepared in different structures using the same equipment, reduced-pressure chemical vapor deposition (RPCVD), and the samples annealed in $N_2$, forming gas (FG), and $O_2$ were compared with the unannealed (deposited and only cleaned) samples to confirm the improvements in Ge quality. To evaluate the thin-film quality, room-temperature photoluminescence (PL) measurements were performed. Among the compared samples, the $O_2$-annealed samples showed the strongest PL signals, regardless of the sample structures, which shows that ex-situ RTA in the $O_2$ environment would be an effective technique for the surface treatment of Ge in fabricating Ge devices for optical computing systems.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.658-665
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• 2014

The neural stimulators have been employed to the visual prostheses system based on the functional electrical stimulation (FES). Due to the size limitation of the implantable device, the smaller area of the unit current driver pixel is highly desired for higher resolution current stimulation system. This paper presents a 16-channel compact current-mode neural stimulator IC with digital to analog converter (DAC) sharing scheme for artificial retinal prostheses. The individual pixel circuits in the stimulator IC share a single 6 bit DAC using the sample-and-hold scheme. The DAC sharing scheme enables the simultaneous stimulation on multiple active pixels with a single DAC while maintaining small size and low power. The layout size of the stimulator circuit with the DAC sharing scheme is reduced to be 51.98 %, compared to the conventional scheme. The stimulator IC is designed using standard $0.18{\mu}m$ 1P6M process. The chip size except the I/O cells is $437{\mu}m{\times}501{\mu}m$.