• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.8A
• /
• pp.820-829
• /
• 2006

IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Due to the request for high performance of current mobile systems, embedded SoC design needs a multi-processor to manage problems of high complexity and the data processing such as multimedia, DMB and image processing in real time. Interface module for communication between system buses and processors are required, since many IPs employ different protocols. High performance processors require interface module to minimize the latency of data transmission during read-write operation and to enhance the performance of a top level system. This paper proposes an automatic interface generation system based on FSM generated from the common protocol description sequence of a bus and an IP. The proposed interface does not use a buffer which stores data temporally causing the data transmission latency. Experimental results show that the area of the interface circuits generated by the proposed system is reduced by 48.5% on the average, when comparing to buffer-based interface circuits. Data transmission latency is reduced by 59.1% for single data transfer and by 13.3% for burst mode data transfer. By using the proposed system, it becomes possible to generate a high performance interface circuit automatically.

• Journal of KIISE:Computer Systems and Theory
• /
• v.33 no.9
• /
• pp.592-607
• /
• 2006

This paper proposes a technique to select processors and hardware IPs and to map the tasks into the selected processing elements, aming to achieve high performance with minimal system cost when multitask applications with real-time constraints are run on a multicore SoC. Such technique is called to 'Hardware-Software Cosynthesis Technique'. A cosynthesis technique was already presented in our early work [1] where we divide the complex cosynthesis problem into three subproblems and conquer each subproblem separately: selection of appropriate processing components, mapping and scheduling of function blocks to the selected processing component, and schedulability analysis. Despite good features, our previous technique has a serious limitation that a task monopolizes the entire system resource to get the minimum schedule length. But in general we may obtain higher performance in multitask multicore system if independent multiple tasks are running concurrently on different processor cores. In this paper, we present two mapping techniques, task mapping avoidance technique(TMA) and task mapping pinning technique(TMP), which are applicable for general cases with diverse operating policies in a multicore environment. We could obtain significant performance improvement for a multimedia real-time application, multi-channel Digital Video Recorder system and for randomly generated multitask graphs obtained from the related works.

• The KIPS Transactions:PartC
• /
• v.8C no.6
• /
• pp.847-854
• /
• 2001

The Web continues to grow fast rate in both a large aclae volume of traffic and the size and complexity of Web sites. Along with growth, the complexity of tasks such as Web site design Web server design and of navigating simply through a Web site have increased. An important input to these design tasks is the analysis of how a web site is being used. The is paper proposes a Page logging System(PLS) identifying reliably user sessions required in Web mining system PLS consists of Page Logger acquiring all the page accesses of the user Log processor producing user session from these data, and statements to incorporate a call to page logger applet. Proposed PLS abbreviates several preprocessing tasks which spends a log of time and efforts that must be performed in Web mining systems. In particular, it simplifies the complexity of transaction identification phase through acquiring directly the amount of time a user stays on a page. Also PLS solves local cache hits and proxy IPs that create problems with identifying user sessions from Web sever log.

• Journal of KIISE:Computer Systems and Theory
• /
• v.34 no.8
• /
• pp.327-336
• /
• 2007

Lots of effort toward design optimizations have been paid for a cost-effective system design in various ways from a transistor level to RTL designs. In this paper, we propose a bit level optimization of an adder design for expanding its design space. For the bit-level optimization, a heterogeneous adder organization utilizing a mixture of carry propagation schemes is proposed to design a delay-area efficient adder which were not available in an ordinary design space. Then, we develop an optimization method based on Integer Linear Programming to search the expanded design space of the heterogeneous adder. The novelty of the Proposed architecture and optimization method is introducing a bit level reconstruction/recombination of IPs which have same functionality but different speed and area characteristics for producing more find-grained delay-area optimization.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.1
• /
• pp.76-84
• /
• 2009

This paper proposes a SOC platform which is eligible for education and application SOC design. The platform, fully synthesizable and reconfigurable, includes the OpenRISC embedded processor, some basic peripherals such as GPIO, UART, debug interlace, VGA controller and WISHBONE interconnect. The platform uses a set of development environment such as compiler, assembler, debugger and RTOS that is built for HW/SW system debugging and software development. Designed SOC, IPs and Testbenches are described in the Verilog HDL and verified using commercial logic simulator, GNU SW development tool kits and the FPGA. Finally, a multimedia SOC derived from the SOC platform is implemented to ASIC using the Magnachip cell library based on 0.18um 1-poly 6-metal technology.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.22 no.2
• /
• pp.302-313
• /
• 2018

As the demand for indoor location recognition system has been rapidly increased in accordance with the increasing use of smart devices and the increasing use of augmented reality, indoor positioning systems(IPS) using BLE (Bluetooth Lower Energy) beacons and UWB (Ultra Wide Band) have been developed. In this paper, a positioning plate is generated by using trilateration technique based on BLE Beacon and using RSSI (Received Signal Strength Indicator). The resultant value is used to calculate the PDR-based coordinates using the positioning element of the Inertial Measurement Unit sensor, We propose a precise indoor positioning algorithm that combines RSSI and PDR technique. Based on the plate algorithm proposed in this paper, the experiment have done at large scale indoor sports arena and airport, and the results were successfully verified by 65% accuracy improvement with average 2.2m error.

• The Journal of Advanced Prosthodontics
• /
• v.12 no.3
• /
• pp.150-156
• /
• 2020

PURPOSE. The aim of this study was to evaluate the effect of different surface finishing processes on the color stabilities of lithium disilicate glass-ceramics, zirconia-reinforced lithium silicate ceramics, and resin nanoceramics after artificial ageing. MATERIALS AND METHODS. 216 samples were prepared from 3 different CAD/CAM materials (LAVA Ultimate, IPS e.max CAD, VITA Suprinity) with A1 HT color at a size of 14 × 12 mm and a thickness of 0.5 ± 0.05 mm. Color measurements of the samples were performed with a spectrophotometer using color parameters and CIE Lab color system on a gray backing between baseline color and after 5000 cycles of artificial ageing in 4 stages (i.e. the first measurement before the treatment, the second measurement after polishing, the third measurement after cement application, and the fourth measurement after artificial ageing). The results were evaluated using the Variance analysis and Fisher's LSD test. RESULTS. Resin nanoceramics (LU) exhibited higher color change values than zirconia-reinforced lithium silicate (VS) and lithium disilicate (EC) ceramics after artificial ageing. Manual polishing and glazing resulted in similar color change for LU and VS (P>.05). In the EC group, glazing provided statistically different results as compared to the manual polishing and control groups (P<.05). Among the ceramic groups, color change values of the subgroup, which was treated by glazing, of the zirconia-reinforced lithium silicate (VS) and lithium disilicate (EC) samples were below the clinically acceptable level (ΔE < 3.5). CONCLUSION. The lowest color change for all stages was observed in Vita Suprinity.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2004.08a
• /
• pp.1058-1061
• /
• 2004

Recently, According to companies of TFT LCD are making large sized products more and more. In the vortex of Products with a monitor and LCD TV is applied in a technique of a high viewing angle(FFS, IPS, VA). Also, as a high luminance, high speed response time, high degree of a color purity, and so on are continuing to develop a high performance, it is necessary to improve a specific character of high luminance that apply to LCD TV as a LCD BLU. Because a LCD panel for TV usually has a lower resolution that compare to a monitor, the structure of present backlight system can't put out its power even though it has a merit in transmission. Therefore, the examination of improvement about the high luminance direct typed BLU for LCD TV that presupposes several uses of CCFL(Cold Cathode Fluorescent Lamp) or EEFL(External Electrode Fluorescent Lamp)is actively being progressed. Although it is necessary to increase the number of lamps for applying high performance by the direct type, in this case, because we can design the character of luminance for adoption of high performance. We can satisfy with a level of luminance for LCD TV. Accordingly, we analyzed a change of the number of CCFL, mechanical and optical character to produce the direct typed backlight in 32inches spec. Consequently, we achieved luminance of 6597nit,which was including polarization film, and secured the standard for LCD TV.

• The Journal of Advanced Prosthodontics
• /
• v.7 no.3
• /
• pp.224-232
• /
• 2015

PURPOSE. The purpose of this study was to find out the effect of immediate dentin sealing (IDS) on bond strength of ceramic restoration under various thermocycling periods with DBA (dentin bonding agent system). MATERIALS AND METHODS. Fifty freshly extracted human mandibular third molars were divided into 5 groups (1 control and 4 experimental groups) of 10 teeth. We removed enamel layer of sound teeth and embedded them which will proceed to be IDS, using All Bond II. A thermocycling was applied to experimental groups for 1, 2, 7, 14 days respectively and was not applied to control group. IPS Empress II for ceramic was acid-etched with ceramic etchant (9.5% HF) and silane was applied. Each ceramic disc was bonded to specimens with Duo-link, dual curable resin cement by means of light curing for 100 seconds. After the cementation procedures, shear bond strength measurement and SEM analysis of the fractured surface were done. The data were analyzed with a one-way ANOVA and Tukey multiple comparison test (${\alpha}$=.05). RESULTS. There were no statistically significant differences between 4 experimental groups and control group, however the mean value started to decrease in group 7d, and group 14d showed the lowest mean bond strength in all groups. Also, group 7d and 14d showed distinct exposed dentin and collapsed hybrid layer was observed in SEM analysis. CONCLUSION. In the present study, it can be concluded that ceramic restorations like a laminate veneer restoration should be bonded using resin cement within one week after IDS procedure.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.5 no.7
• /
• pp.1329-1345
• /
• 2011

After the 9.11 terror attack, lawful Interception (LI) has emerged as an important tool for anti-terrorist activity. Law enforcement agents and administrative government bodies effectively monitor suspicious target users of permanent IP-based network devices by LI in Packet Data Networks (PDNs). However, it is difficult to perform LI in monitoring migrating users from a location to another, who change their IPs due to the proliferation of portable Internet devices enabling 3G IP Multimedia Subsystems (IMS). The existing, manual handover technique in 3G IMS makes it even more difficult to continue the LI activities due to time-lag reissuance of LI authority warrants when the target users move to a new LI jurisdiction via a roaming service. Our proposed model is a seamless LI handover mechanism in 3G IMS to support mobility detection of the target users. The LI warrants are transferred to the new LI agent automatically with the target users when they move to a new LI jurisdiction. Thus, time-lag human intervention of reissuance of the LI warrants is removed and enables the LI authorities to continue monitoring. In the simulation of our proposed mechanism, the quality of lawful interception achieves a mean score of over 97.5% out of the possible 100% maximum score, whereas the quality of the existing mechanism has a mean score of 22.725%.