• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.981-985
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• 2004

In this paper we designed the motor control IP Core and evaluate its quality from the viewpoint of IP reuse. The most attractive merit of this methodology, so called IP-based hardware design, is hardware reuse. Although various vendors designed hardware with the same specification and got the same functional results, all that IPs is not the same quality in the reuse aspect. As tremendous calls for SoC have been increased, associated research about IP quality standard, VSIA(Virtual Socket Interface Alliance) and STARC(Semiconductor Technology Academic Research Center), has been doing best to make the IP quality evaluation system. And they made what conforms to objective IP design standard. We suggest the methodology to evaluate our own designed motor control IP quality with this standard. To attain our goal, we designed motor control IP that could control the motor velocity and position with feedback compensation algorithm. This controller has some IP blocks : digital filter, quadrature decoder, position counter, motion compensator, and PWM generator. Each block's functionality was verified by simulator ModelSim and then its quality was evaluated. To evaluate the core, We use Vnavigator for lint test and ModelSim for coverage check. During lint process, We adapted the OpenMORE's rule based on RMM (Reuse Methodology Manual) and it could tell us our IP's quality in a manner of the scored value form. If it is high, its quality is also high, and vice versa. During coverage check ModelSim-SE is used for verifying how our test circuits cover designs. This objective methods using well-defined commercial coverage metrics could perform a quantitative analysis of simulation completeness. In this manner, We evaluated the designed motor control IP's quality from the viewpoint of reuse. This methodology will save the time and cost in designing SoC that should integrate various IPs. In addition to this, It can be the guide for comparing the equally specified IP's quality. After all, we are continuously looking forward to enhancing our motor control IP in the aspect of not only functional perfection but also IP reuse to prepare for the SoC-Compliant motor control IP design.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.924-927
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• 2009

IP reuse technology, for the sake of out-performance and the reduction of development period of IT-SoC is the most essential factor for the sound growth of SoC industry. As for this IP reuse technology, it is very important to decide the proper specification and the standardization of the requirement from the companies, as well as to develop our own domestic technological know-how which does not depend on import. In this study, we propose to analyze a security core IP with pure domestic technological know-how, mentioning an example from $CAST_{TM}$, which presently is an American company costing royalty.

• Journal of IKEEE
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• v.18 no.3
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• pp.349-355
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• 2014

In semiconductor IP reuse, precise understanding of semiconductor IP interfaces is essential for integrated chip design. However, in general, these interfaces are described in the original designer's description style. Furthermore, their description method are not unified, so it is very difficult for the chip integration designer to understand them. This paper proposes a standardized description method of semiconductor IP interfaces. It consists of 9 items such as IP information, description level, model provision, data type, interface information, port information, signal information, protocol information, and source file. The proposed method helps the chip integration designer to understand semiconductor IP interfaces and to integrate them into a single chip.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.172-175
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• 2000

In this paper, we address the requirement of VHDL parser for design rule checker, and the structure and implementing method of design rule checker which checks if IP design is valuable to reuse. This checker builds the grammar trees from the design rules, and the internal graphs representation from IP design data. It maps the nodes of the grammar trees and the internal graphs to check if it violates the design rules. The design rule checker can do the cross reference between source codes and error messages to find error position easy.

• Journal of IKEEE
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• v.18 no.3
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• pp.341-348
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• 2014

When several resuable semiconductor IPs are connected and implemented into an integrated chip, each semiconductor IP should provide code files for synthesis and interface modeling files for simulation and verification. However, description methods and levels of abstraction of interface modeling files are different because these semiconductor IPs are designed by different designers, which makes some problems in simulation and verification. This paper proposes a standardized modeling method of semiconductor IP interfaces. It restricts semiconductor IP interfaces to several predefined level of abstraction. The proposed method helps the chip integration designer to easily connect different semiconductor IPs and to simulate and verify them.

• The KIPS Transactions:PartC
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• v.12C no.4 s.100
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• pp.481-488
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• 2005

The Mobile W provides an efficient and scalable mechanism for host mobility within the Internet. However, the mobility implies higher security risks than static operations in fixed networks. In this paper, the Mobile IP has been adapted to allow AAA protocol that supports authentication, authorization, and accounting(AAA) for security and collection for accounting information of network usage by mobile nodes(MNs). For this goal, we Propose the boundary tone overlapped network structure while solidifying the security for the authentication of an MN. That is, the Proposed scheme delivers the session keys at the wired link for MN's security instead of the wireless one, so that it provides a fast and seamless handoff mechanism. According to the analysis of modeling result, the proposed mechanism compared to the existing session key reuse method is up to about $40\%$ better in terms of normalized surcharge for the handoff failure rate that considers handoff total time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.769-770
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• 2011

This paper presented a method constructing the ITSoC(Information Technology System-on-Chip). In order to implement the ITSoC, designers are increasing relying on reuse of intellectual property(IP) blocks. Since IP blocks are pre-designed and pre-verified, the designer can concentrate on the complete system without having to worry about the correctness or performance of the individual components. Also, embedded core in an ITSoC access mechanisms are required to test them at the system level. That is the goal, in theory. In practice, assembling an ITSoC using IP blocks is still an error-prone, labor-intensive and time-consuming process. This paper discuss the main challenge in ITSoC designs using IP blocks and elaborates on the methodology and tools being put in place for addressing the problem. It explains ITSoC architecture and gives algorithmic details on the high-level tools being developed for ITSoC design.

• The Transactions of the Korea Information Processing Society
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• v.4 no.8
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• pp.1961-1974
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• 1997

WWW has accepted widely to the who wants the hypermedia-based internet services. And WWW introduces intranet environment which consists of the networks supporting TCP/IP and HTTP protocol for processing the task of company inside that. Intranet application should support not only acquiring the informations, but also producing, modifying and deleting the ones. But since previous hypermedia development methods lack modeling behavior of system and reuse, we need a new method for intranet application. In this thesis, we have proposed the OOIDM(Object Oriented Intranet application Development Method)supporting modeling behavior of system and reuse. And we have proposed the design patterns available for the intranet domain in order to reuse the design information. And we introduces a case study about OOIDM applying design patterns. Adaptation of design patterns to intranet domain gives us much benefits. Design patterns make it easier to reuse the successful design, architecture and reducing the design decisions.

• Smart Media Journal
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• v.3 no.4
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• pp.9-15
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• 2014

A virtual platform models a processor core and the peripheral devices constituting the SoC in software. Major companies utilize a variety of platforms for product development with optimal SW+SoC integrated system architecture design and IP reuse based Top-Down design flow using a virtual platform. In this paper, we propose a virtual platform based on OpenRISC, an open source RISC based core. The proposed virtual platform supports high speed emulation of approximately 20 MIPS using DBT (Dynamic Binary Translation).

• Proceedings of the Korea Information Processing Society Conference
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• 2000.04a
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• pp.1089-1094
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• 2000

소형 고성능 가전기기를 실현하기 위한 다기능 고집적의 실리콘화에 대응하기 위하여 반도체 업계는 SoC(System On a Chip) 설계, 반도체 지적 재산권인 IP(Intellectual Property)에 관한 연구를 두개의 핵심 연구 항목으로 설정하여 진행되어 왔다. 반도체 레이아웃 이식 자동화 시스템은 설계 재활용(Design Reuse), IP의 실용화와 확산을 위한 핵심 연구 과제 중의 하나로써, Time-To-Market 과 Time-To-Money 를 동시에 가능토록 하는 근간의 기술이 된다. 본 연구는 정확하고 고속의 IP내의 반도체 소자 인식 알고리즘, 그래프를 이용한 제한 조건의 구현과 해석, 향상된 컴팩션(Compaction) 알고리즘의 연구로 말미암아 기존의 연구 결과 대비 평균 20배의 속도 향상과 평균 41%의 메모리만을 사용함으로써 경쟁 기술 대비 월등한 우위를 보이고 있다. 이로써, 대형의 반도체 설계 도면의 처리를 가능하도록 하였으며, 반도체 IP의 응용성(flexibility)을 부여 함으로써, IP의 재활용의 기초 연구와 SoC 설계 확산에 지렛대 역할을 하는 연구가 되리라고 예측한다.