• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 춘계학술발표강연 및 논문개요집
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• pp.107-107
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• 2003

원자층 증착(ALD, Atomic Layer Deposition)기술은 기판 표면에서의 self-limiting reaction을 통해 매우 얇은 박막을 형성할 수 있고, 두께 및 조성 제어를 정확히 할 수 있으며, 복잡한 형상의 기판에서도 100%에 가까운 step coverage를 얻을 수 있어 초미세패턴의 형성과 매우 얇은 두께에서 균일한 물리적, 전기적 특성이 요구되는 초미세 반도체 공정에 적합하다. 특히 반도체의 logic 및 memory 소자의 gate 공정에서 절연막과 보호막으로, 그리고 배선공정에서는 층간절연막(ILD, Inter Layer Dielectric)으로 사용하는 silicon oxide 박막에 적용될 경우, LPCVD 방법에 비해 낮은 온도에서 증착이 가능해 boron과 같은 dopant들의 확산을 최소화하여 transistor 특성 향상이 가능하며, PECVD 방법에 비해 전기적·물리적 특성이 월등히 우수하고 대면적 uniformity 증가가 기대된다. 본 연구에서는 자체적으로 설계 및 제작한 장비를 이용하여 silicon oxide 박막을 ALD 방법으로 증착하고 그 특성을 살펴보았다. 먼저, cycle 수에 따른 증착 박막 두께의 linearity를 통해서 원자층 증착(ALD)임을 확인할 수 있었으며, reactant exposure(L)와 증착 온도에 따른 deposition rate 변화를 알아보았다 Elipsometer를 이용해 증착된 silicon oxide 박막의 두께 및 굴절률과 그 uniformity를 관찰하였고, AES 및 XPS 분석 장비로 박막의 조성비와 불순물 성분을 살펴보았으며, 증착 박막의 치밀성 평가를 위해 HF etchant로 wet etch rate를 측정하여 물리적 특성을 정리하였다. 특히, 기존의 박막 증착 방법인 LPCVD와 PECVD에 의한 silicon oxide박막의 물성과 비교, 평가해 보았다. 나아가 적절한 촉매 물질을 선정하여 원자층 증착(ALD) 공정에 적용하여 그 효과도 살펴보았다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.362-363
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• 2005

The objectives of this paper are to achieve good planarization of the deposited film and to improve deposition efficiency of multi-layer structures by using surface-micromaching process in MEMS technology. Planarization characteristic of poly-Si film deposited on thin oxide layer with MEMS structures is evaluated with different slurries. Patterns used for this research have shapes of square, density, line, hole, pillar, and micro engine part. Advantages and disadvantages of CMP for MEMS structures are observed respectively by using the test patterns with structures larger than 1 um line width. Preliminary tests for material selectivity of poly-Si and oxide are conducted with two types of slurries: ILD1300 and Nalco2371. And then, the experiments were conducted based on the pretest.

• Transactions on Electrical and Electronic Materials
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• 제7권4호
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• pp.157-162
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• 2006

Chemical-mechanical polishing (CMP), one of the dominant technology for ULSI planarization, is used to flatten the micro electro-mechanical systems (MEMS) structures. The objective of this paper is to achieve good planarization of the deposited film and to improve deposition efficiency of subsequent layer structures by using surface-micromachining process in MEMS technology. Planarization characteristic of poly-Si film deposited on thin oxide layer with MEMS structures is evaluated with different slurries. Patterns used for this research have shapes of square, density, line, hole, pillar, and micro engine part. Advantages of CMP process for MEMS structures are observed respectively by using the test patterns with structures larger than 1 urn line width. Preliminary tests for material selectivity of poly-Si and oxide are conducted with two types of silica slurries: $ILD1300^{TM}\;and\;Nalco2371^{TM}$. And then, the experiments were conducted based on the pretest. A selectivity and pH adjustment of slurry affected largely step heights of MEMS structures. These results would be anticipated as an important bridge stone to manufacture MEMS CMP slurry.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제51권7호
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• pp.311-315
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• 2002

Chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD), inter-level dielectric (ILD) layers of multi-layer interconnections. In this paper, we studied the characteristics of polishing pad, which can apply shallow trench isolation (STI)-CMP process for global planarization of multi-level interconnection structure. Also, we investigated the effects of different sets of polishing pad, such as soft and hard pad. As an experimental result, hard pad showed center-fast type, and soft pad showed edge-fast type. Totally, the defect level has shown little difference, however, the counts of scratch was detected less than 2 on JR111 pad. Through the above results, we can select optimum polishing pad, so we can expect the improvements of throughput and device yield.

• 마이크로전자및패키징학회지
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• 제21권4호
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• pp.63-68
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• 2014

For a nanoscale Cu/low-k wafer, inter-layer dielectric (ILD) and metal layers peelings, cracks, chipping, and delamination are the most common dicing defects by traditional diamond blade saw process. Sidewall void in sawing street is one of the key factors to bring about cracks and chipping. The aim of this research is to evaluate laser grooving & mechanical sawing parameters to eliminate sidewall void and avoid top-side chipping as well as peeling. An ultra-fast pico-second (ps) laser is applied to groove/singulate the 28-nanometer node wafer with Cu/low-k dielectric. A series of comprehensive parametric study on the recipes of input laser power, repetition rate, grooving speed, defocus amount and street index has been conducted to improve the quality of dicing process. The effects of the laser kerf geometry, grooving edge quality and defects are evaluated by using scanning electron microscopy (SEM) and focused ion beam (FIB). Experimental results have shown that the laser grooving technique is capable to improve the quality and yield issues on Cu/low-k wafer dicing process.

• Transactions on Electrical and Electronic Materials
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• 제1권1호
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• pp.40-44
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• 2000

Metal-ferroelectric-insulator-semoiconductor field effect transistor (MFISFETs) were fabricated using CMOS processes. The Pt/SBT/NO combined layers were etched for forming a conformal gate by using Ti/Cr metal masks and a two step etching method, By the method, we were able to fabricate a small-sized gate with the dimension of $16/4{\mu}textrm{m}$ in the width/length of gate. It has been chosen the non-self aligned source and drain implantation process, We have deposited inter-layer dielectrics(ILD) by low pressure chemical vapor deposition(LPCVD) at $380^{circ}C$ after etching the gate structure and the threshold voltage of p-channel MFISFETs were about 1.0 and -2.1V, respectively. It was also observed that the current difference between the $I_{ON}$(on current) and $I_{OFF}$(off current) that is very important in sensing margin, is more that 100 times in $I_{D}-V_{G}$ hysteresis curve.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 춘계학술대회 논문집 센서 박막재료 반도체 세라믹
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• pp.149-153
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• 2003

Chemical mechanical polishing (CMP) technology for global planarization of multi-level inter-connection structure has been widely studied for the next generation devices. CMP process has been paid attention to planarized pre-metal dielectric (PMD), inter-layer dielectric (ILD) interconnections. Expecially, shallow trench isolation (STI) used to CMP process on essential. Recently, the direct STI-CMP process without the conventional complex reverse moat etch process has established by using slurry additive with the high selectivity between $SiO_2$ and $Si_3N_4$ films for the purpose of process simplification and n-situ end point detection(EPD). However, STI-CMP process has various defects such as nitride residue, tom oxide and damage of silicon active region. To solve these problems, in this paper, we studied the planarization characteristics using a high selectivity slurry(HSS). As our experimental results, it was possible to achieve a global planarization and STI-CMP process could be dramatically simplified. Also we estimated the reliability through the repeated tests with the optimized process conditions in order to identify the reproducibility of HSS STI-CMP process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.81-81
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• 2007

Chemical mechanical polishing (CMP) 공정은 deep 서브마이크론 집적회로의 다층배선구조률 실현하기 위해 inter-metal dielectric (IMD), inter-layer dielectric layers (ILD), pre-metal dielectric (PMD) 층과 같은 절연막 외에도 W, Al, Cu와 같은 금속층을 평탄화 하는데 효과적으로 사용되고 있으며, 다양한 소자 제작 및 새로운 물질 등에도 광범위하게 응용되고 있다. 하지만 Cu damascene 구조 제작으로 인한 CMP 응용 과정에서, 기계적으로 깨지기 쉬운 65 nm의 소자 이하의 구조에서 새로운 저유전상수인 low-k 물질의 도입으로 인해 낮은 하력의 기계적 연마가 필요하게 되었다. 본 논문에서는 전기화학적 기계적 연마 적용을 위해, I-V 특성 곡선을 이용하여 active, passive, transient, trans-passive 영역의 전기화학적 특성을 알아보았으며, Cu 막의 표면 형상을 알아보기 위해 scanning electron microscopy (SEM) 측정과 energy dispersive spectroscopy (EDS) 분석을 통해 금속 화학적 조성을 조사하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.119-120
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• 2007

반도체 공정에서 사용되는 ILD막질 중 oxy-nitrde(SiON) film은 contact etch stopper, photo공정을 위한 ARL(anti-reflection lay떠 그리고, 후속공정의 plasma damage에 대한 blocking layer로서의 역할을 담당하며 많은 공정에 널리 사용되고 있다. 그러나 막질 자체의 불완전성 (trap site, dangling bond)에 의해 cell current instability(CCI) 특성을 악화 시킬 수 있어 이에 대한 원인규명 및 대책이 요구되었다. 본 연구는 미국 S사(社) super flash memory에서 oxy-nitride 막질 증착 시의 gas flow량에 따른 CCI 특성변화를 연구하고 최적의 공정조건을 제시하고자 한다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.10-10
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• 2008

Silicide is inevitable for CMOSFETs to reduce RC delay by reducing the sheet resistance of gate and source/drain regions. Ni-silicide is a promising material which can be used for the 65nm CMOS technologies. Ni-silicide was proposed in order to make up for the weak points of Co-silicide and Ti-silicide, such as the high consumption of silicon and the line width limitation. Low resistivity NiSi can be formed at low temperature ($\sim500^{\circ}C$) with only one-step heat treat. Ni silicide also has less dependence of sheet resistance on line width and less consumption of silicon because of low resistivity NiSi phase. However, the low thermal stability of the Ni-silicide is a major problem for the post process implementation, such as metalization or ILD(inter layer dielectric) process, that is, it is crucial to prevent both the agglomeration of mono-silicide and its transformation into $NiSi_2$. To solve the thermal immune problem of Ni-silicide, various studies, such as capping layer and inter layer, have been worked. In this paper, the Ni-silicide utilizing Pd stacked layer (Pd/Ni/TiN) was studied for highly thermal immune nano-scale CMOSFETs technology. The proposed structure was compared with NiITiN structure and showed much better thermal stability than Ni/TiN.