• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.119-120
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• 2008

ILD CMP process has been well accepted for the planarization of the dielectric oxide film and becomes a critical process in ULSI manufacturing due to the rapid shrinkage of the design rule for the device. In total manufacturing process steps for a device, the proportion of ILD CMP process has been gradually increased. Ever since ILD CMP has been introduced, the scratches have been a major defects on polished surfaces which cause the electrical shorts between vias or metal lines [1,2]. It was reported that micro-scratches are caused by large, irregularly shaped particles during CMP process. Therefore, most of the CMP users have used < 5 m POU filter to remove and reduce the scratch source from the slurry. However, the scratch has always been the biggest concern in ILD polishing whatever preventive actions are taken. Silica and ceria slurries are widely used for ILD CMP process. There are not much differences in generated scratches and their formation mechanism. In this study, the scratches were investigated as a function of polishing conditions with possible explanation on formation mechanism in ILD CMP.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.1121-1124
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• 2001

In this study, we verify th effects of pattern density on interlayer dielectric chemical mechanical polishing process based on the analysis of Preston's equation and confirm this analysis by several experiments. Appropriate modeling equation, transformed form Preston's equations used in glass polishing, will be suggested and described the effects of this modeling during pattern wafer ILD CMP. Results indicate that the modeling is well agreed to middle density structure of the die in pattern wafer, but has some error in low and high density structure of the die. Actually, the die used in Fab, was designed to have a appropriate density, therefore this modeling will be suitable for estimating the results of ILD CMP.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.10
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• pp.812-816
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• 2000

It is very important to understand the correlation of between inter dielectric(ILD) CMP process and various facility factors supplied to equipment to equipment system. In this paper, the correlation between the various facility factors supplied to CMP equipment system and ILD-CMP process was studied. To prevent the partial over-polishing(edge hot-spot) generated in the wafer edge area during polishing, we analyze various facilities supplied at supply system. With facility shortage of D.I water(DIW) pressure, we introduced an adding purified $N_2$(P$N_2$)gas in polishing head cleaning station for increasing a cleaning effect. DIW pressure and P$N_2$gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. We estimated two factors (DIW pressure and P$N_2$gas) for the improvement of CMP process. Especially, we obtained a uniform planarity in patterned wafer and prohibited more than 90% wafer edge over-polishing. In this study, we acknowledged that facility factors supplied to equipment system played an important role in ILD-CMP process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.31-34
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• 2000

It is very important to understand the correlation of between inter layer dielectric(ILD) CMP process and various facility factors supplied to equipment system. In this paper, the correlation between the various facility factors supplied to CMP equipment system and ILD CMP process were studied. To prevent the partial over-polishing(edge hot-spot) generated in the wafer edge area during polishing, we analyzed various facilities supplied at supply system. With facility shortage of D.I. water(DIW) pressure, we introduced an adding purified $N_2(PN_2)$ gas in polishing head cleaning station for increasing a cleaning effect. DIW pressure and PN2 gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. We estimated two factors (DIW pressure and PN2 gas) for the improvement of CMP process. Especially, we obtained a uniform planarity in patterned wafer and prohibited more than 90% wafer edge over-polishing. In this study, we acknowledged that facility factors supplied to equipment system played an important role in ILD-CMP process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.59-59
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• 2009

현재 CMP분야는 광역 평탄화 반도체 소자의 집적화 및 소형화가 진행됨에 따라서 CMP 공정의 중요성은 날로 성장하고 있다. 하지만 이러한 CMP공정은 불가피하게도 scratch, pit, CMP residue와 같은 defect들을 발생시키고 있으며, 점점 선폭이 작아짐에 따라, 이러한 defect들이 반도체 수율에 미치는 영향은 심각해지고 있다. Defect들 중에 특히 scratch는 반도체에 치명적인 circuit failure를 일으키게 된다. 또한 반도체 내구성과 신뢰성을 감소시키게 되고, 누전전류를 증가시키는 등 바람직하지 못한 현상들이 생기게 된다. 본 연구에서는 scratch 와 같은 deflect들을 효율적으로 검출, 분석하고, scratch를 감소시키는데 그 목적이 있다. 본 실험을 위해 8" TEOS wafer와 commercial oxide slurry 및 friction polisher (Poli-500, G&P tech., Korea)를 사용하여 CMP 공정을 진행하였으며, CMP 공정조건은 각각 80rpm/80rpm/1psi(Platen speed/Head speed/Pressure)에서 1분 동안 연마를 한 후 scratch 발생 경향을 살펴보았다. CMP 후 wafer위에 오염되어 있는 slurry residue들을 제거하기 위해 SC-1, HF 세정을 이용하여 최적화된 post-CMP 공정기술을 제안하였다. Scratch 검출 및 분석을 위해 wafer surface analyzer (Surfscan 6200, Tencor, USA)와 optical microscope (LV100D, Nicon, Japan)를 사용하였다. CMP 공정 변수들에 따른 scratch 발생정도를 비교하였으며, scratch 발생 요인들에 따른 scratch 형태 및 발생정도를 살펴보았다. 최적화된 post-CMP 세정 조건은 메가소닉과 함께 SC-1 세정을 실시하여 slurry residue들을 제거한 후, HF 세정을 실시하여 잔여 오염물들을 제거하고 검출이 용이하도록 scratch를 확장시킬 수 있도록 제안하였으며, 100%의 particle removal efficiency (PRE)를 얻을 수 있었다. 실제 CMP 공정후 post-CMP 세정 단계별 scratch 개수를 측정한 결과, SC-1 세정 후 약 220개의 scratch가 검출되었으며, 검출되지 않았던 scratch가 HF 세정 후 확장되어 드러남에 따라 약 500개의 scratch 가 검출되었다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.23-23
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• 2011

Chemical-Mechanical Planarization (CMP) 공정이란 화학적 반응 및 기계적인 힘이 복합적으로 작용하여 표면을 평탄화하는 공정이다. 이러한 CMP 공정은 반도체 산업에서 회로의 고집적화와 다층구조를 형성하기 위하여 도입되었으며 반도체 제조를 위한 필수공정으로 그 중요성이 강조되고 있다. 특히 최근에는 Inter-Level Dielectric (ILD)의 형성과 Shallow Trench Isolation (STI) 공정에서실리콘 산화막을 평탄화하기 위한 CMP 공정에 대해 연구가 활발히 이루어지고 있다. 그러나 CMP 공정 후 scratch, pitting corrosion, contamination 등의 Defect가 발생하는 문제점이 존재한다. 이 중에서도 scratch는 기계적, 열적 스트레스에 의해 생성된 패드의 잔해, 슬러리의 잔유물, 응집된 입자 등에 의해 표면에 형성된다. 반도체 공정에서는 다양한 종류의 실리콘 산화막이 사용되고 gks이러한 실리콘 산화막들은 종류에 따라 경도가 다르다. 따라서 실리콘 산화막의 경도에 따른 CMP 공정 및 이로 인한 Scratch 발생에 관한 연구가 필요하다고 할 수 있다. 본 연구에서는 scratch 형성의 거동을 알아보기 위하여 boronphoshposilicate glass (BPSG), plasma enhanced chemical vapor deposition (PECVD) tetraethylorthosilicate (TEOS), high density plasma (HDP) oxide의 3가지 실리콘 산화막의 기계적 성질 및 이에 따른 CMP 공정에 대한 평가를 실시하였다. CMP 공정 후 효율적인 scratch 평가를 위해 브러시를 이용하여 1차 세정을 실시하였으며 습식세정방법(SC-1, DHF)으로 마무리 하였다. Scratch 개수는 Particle counter (Surfscan6200, KLA Tencor, USA)로 측정하였고, 광학현미경을 이용하여 형태를 관찰하였다. Scratch 평가를 위한 CMP 공정은 실험에 사용된 3가지 종류의 실리콘 산화막들의 경도가 서로 다르기 때문에 동등한 실험조건 설정을 위해 동일한 연마량이 관찰되는 조건에서 실시하였다. 실험결과 scratch 종류는 그 형태에 따라 chatter/line/rolling type의 3가지로 분류되었다 BPSG가 다른 종류의 실리콘 산화막에 비해 많은 수에 scratch가 관찰되었으며 line type이 많은 비율을 차지한다는 것을 확인하였다. 또한 CMP 공정에서 압력이 증가함에 따라 chatter type scratch의 길이는 짧아지고 폭이 넓어지는 것을 확인하였다. 본 연구를 통해 실리콘 산화막의 경도에 따른 scratch 형성 원리를 파악하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.05b
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• pp.30-33
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• 2001

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectrics, which can apply to employed in integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of free-defects in inter-level dielectrics (ILD). Especially, defects like micro-scratch lead to severe circuit failure, and affects yield. CMP slurries can contain particles exceeding $1{\mu}m$ size, which could cause micro-scratch on the wafer surface. The large particles in these slurries may be caused by particle agglomeration in slurry supply line. To reduce these defects, slurry filtration method has been recommended in oxide CMP. In this work, we have studied the effects of filtration and the defect trend as a function of polished wafer count using various filters in inter-metal dielectric(IMD)-CMP. The filter installation in CMP polisher could reduce defect after IMD-CMP. As a result of micro-scratches formation, it shows that slurry filter plays an important role in determining consumable pad lifetime.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.7
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• pp.557-561
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• 2001

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integraded circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics (ILD). Especially, defects such as micro-scratch lead to severe circuit failure which affect yield. CMP slurries can contain particles exceeding 1㎛ in size, which could cause micro-scratch on the wafer surface. The large particles in these slurries may be caused by particles agglomeration in slurry supply line. To reduce these defects, slurry filtration method has been recommended in oxide CMP. In this work, we have studied the effects of filtration and the defect trend as a function of polished wafer count using various filters in inter-metal dielectrics(IMD)-CMP process. The filter installation in CMP polisher could reduce defects after IMD-CMP process. As a result of micro-scratch formation, it is shown that slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. We have concluded that slurry filter lifetime is fixed by the degree of generating defects.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.935-938
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• 1997

Recently, the minimum line width shows a tendency to decrease and the multi-level increase in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. But there are several defects in CMP such as micro-scratches, abrasive contaminations, and non-uniformity of polished wafer edges. Wet etching include of Spin-etching can improve he defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(INterlayer-Dielectric) was removed by CMP and wet-etching methods in order to investigate the superiority of wet etching mechanism. In the thin film wafer, the results were evaluated at a viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And pattern step height was also compared for planarization characteristics of the patterned wafer.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.9 s.240
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• pp.1276-1281
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• 2005

Compound semiconductors are the semiconductors composed of more than two chemical elements. Lithium Tantalate$K_I$ wafer is used for several optical devices, especially surface acoustic wave(SAW) device. Because of the lithography in SAW device process, $LiTaO_3$ polishing is needed. In this paper, the commercial slurries $(NALC02371^{TM},\; ILD1300^{TM},\;ceria slurry)$ used for chemical mechanical polishing(CMP) were tested, and the most suitable slurry was selected by measuring material removal rate and average centerline roughness$(R_a)$. From these result, it was proven that $ILD1300^{TM}$ was the most suitable slurry for $LiTaO_3$ wafer CMP due to the chemical reaction between solution in slurry and material.