• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.329-332
• /
• 2002

The traditional debug tools for chip tests and software developments need a huge investment and a plenty of time. These problems can be overcome by Embedded Debugger based the JTAG boundary Scan Architecture. Thus, the IEEE 1149.1 standard is adopted by ASIC designers for the testability problems. We designed the RED(Reusable Embedded Debugger) using the JTAG boundary Scan Architecture. The proposed debugger is applicable for not a chip test but also a software debugging. Our debugger has an additional hardware module (EICEM : Embedded ICE Module) for more critical real-time debugging.

• Proceedings of the KIEE Conference
• /
• 2002.11c
• /
• pp.197-200
• /
• 2002

We newly developed the procedures of X-ray Cargo inspection system with acquisition of multi-channel data, analog to digital converter and post logic circuit which is controlled by the FPGA. The IEEE1149.1 standard defines a four-wire serial interface(a fifth wire is optional)to access complex integrated circuits(ICs) such as PLD. This paper describes that Boundary_Scan test method applied to our home made cargo inspection system.

• ETRI Journal
• /
• v.36 no.2
• /
• pp.293-300
• /
• 2014

As the system-on-chip (SoC) design becomes more complex, the test costs are increasing. One of the main obstacles of a test cost reduction is the limited number of test channels of the ATE while the number of pins in the design increases. To overcome this problem, a new test architecture using a channel sharing compliant with IEEE Standard 1149.1 and 1500 is proposed. It can significantly reduce the pin count for testing a SoC design. The test input data is transmitted using a test access mechanism composed of only input pins. A single test data output pin is used to measure the sink values. The experimental results show that the proposed architecture not only increases the number of sites to be tested simultaneously, but also reduces the test time. In addition, the yield loss owing to the proven contact problems can be reduced. Using the new architecture, it is possible to achieve a large test time and cost reduction for complex SoC designs with negligible design and test overheads.

• Journal of the Korea Society of Computer and Information
• /
• v.13 no.4
• /
• pp.87-95
• /
• 2008

In this paper, we developed a selectable observation Point test architecture and test procedure for clocked 4-bit synchronous counter circuit based on boundary scan architecture. To develope, we analyze the operation of Sample/Preload instruction on boundary scan architecture. The Sample/Preload instruction make Possible to snapshot of outputs of CUT(circuit under test) at the specific time. But the changes of output of CUT during normal operation are not possible to observe using Sample/Preload in typical scan architecture. We suggested a selectable observation point test architecture that allows to select output of CUT and to observe of the changes of selected output of CUT during normal operation. The suggested a selectable observation point test architecture and test procedure is simulated by Altera Max 10.0. The simulation results of 4-bit counter shows the accurate operation and effectiveness of the proposed test architecture and procedure.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.6
• /
• pp.70-76
• /
• 2015

This paper introduces an FPGA self-test architecture reusing FPGA boundary scan chain as self-test circuits. An FPGA boundary scan cell is two or three times bigger than a normal boundary scan cell because it is used for configuring the function of input/output pins functions as well as testing and debugging. Accordingly, we analyze the architecture of an FPGA boundary scan cell in detail and design a set of built-in self-test (BIST) circuits in which FPGA boundary scan chain and a small amount of FPGA logic elements. By reusing FPGA boundary scan chain for self-test, we can reduce area overhead and perform a processor based on-board FPGA testing/monitoring. Experimental results show the area overhead comparison and simulation results.

• The KIPS Transactions:PartA
• /
• v.16A no.2
• /
• pp.79-88
• /
• 2009

In boundary scan architecture, test stimuli are shifted in one at a time and applied to the on-chip system logic. The test results are captured into the BSR and are examined by subsequent shifting. In this paper, we developed a continuous capture test architecture and test procedure using TPG based on boundary scan is used to performance test. In this architecture, test patterns of TPG are applied to CUT with system clock rate, and response of CUT is continuously captured by CBSR(Continuous Capture Boundary Scan Register) at the same rate and the captured results is shifted to TDO at the same rate. The suggested a continuous capture test architecture and test procedure is simulated by Altera Max+Plus 10.0. The simulation results shows the accurate operation and effectiveness of the proposed test architecture and procedure.