• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1355-1362
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.132-135
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.31-40
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• 2010

This paper describes a LDPC decoder for IEEE 802.11n wireless LAN standard. The designed processor supports parity check matrix for block length of 1,944 and code rate of 1/2 in IEEE 802.11n standard. To reduce hardware complexity, the min-sum algorithm and layered decoding architecture are adopted. A novel memory reduction technique suitable for min-sum algorithm was devised, and our design reduces memory size to 25% of conventional method. The LDPC decoder processor synthesized with a $0.35-{\mu}m$ CMOS cell library has 200,400 gates and memory of 19,400 bits, and the estimated throughput is about 135 Mbps at 80 MHz@2.5v. The designed processor is verified by FPGA implementation and BER evaluation to validate the usefulness as a LDPC decoder.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.4B
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• pp.360-367
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• 2009

In this paper, we propose a design methodology of IEEE 802.11n MAC which aims to achieve the higher throughput of more than 100Mbps in downlink as measured at the MAC-SAP and present the implementation results of MAC using the proposed design methodology. With our proposed methodology, different from the conventional design flow which has the separate codes for the protocol validation, for the network simulation, and for the system implementation, the unified code can be used for the network simulation and the implementation of software and hardware. Our MAC architecture is partitioned into two parts, Upper-layer MAC and Lower-layer MAC, in order to achieve the high efficiency for the new features of IEEE 802.11n standard. They are implemented in software and hardware respectively. The implemented MAC is tested on ARM based FPGA board.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.363-371
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• 2013

This paper describes a multi-standard LDPC decoder which supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A DFU(decoding function unit) based on sign-magnitude arithmetic is used for hardware reduction. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.13-${\mu}m$ CMOS cell library. It has 312,000 gates and 70,000 bits RAM. The estimated throughput is about 79~210 Mbps at 100 MHz@1.8v.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06d
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• pp.291-293
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• 2012

급격히 증가하는 모바일 디바이스에 의한 모바일 데이터 요구량을 처리하기 위해 가장많이 고려되고 있는 IEEE 802.11의 WLAN은 셀룰러보다 높은 데이터 전송속도를 제공하지만 이동성이 고려되어있지 않다. 이에 본 논문에서는 Enterprise WLAN에서 IEEE 802.21 MIH 표준에 기반하여 Media Independent Information Server (MIIS)로부터 수신된 주변 AP들의 네트워크의 정보를 바탕으로 후보 엑세스 AP 네트워크를 선정 및 WiMAX에 make-before-break 핸드오버하는 방안을 제안한다. 제안하는 방안은 실제 Enterprise WLAN와 Mobile WiMAX 환경에서 이동하는 단말의 시간에 따른 TCP throughput에 대한 성능평가를 하였다. 이를 통해 제안하는 방안의 평균TCP throughput 성능이 9.04Mbits/s으로 기존 방안의 TCP throughput 성능 6.49Mbits/s보다 약 40%향상됨을 확인하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.9A
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• pp.803-813
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• 2005

This paper explores the throughput performance of CSMA/CA-based DCF protocol over frequency-selective, slow Ricean fading channels with both the $E_{b}/N_{o}$ and BER at the MAC layer in the 802.1 la wireless LAN. By exploring the throughput of DCF protocol with the data rate of 6Mbps, 12 Mbps, 24 Mbps and 54 Mbps, we find the fact that the higher the $E_{b}/N_{o}$ be and the less the BER be, the higher the throughput be.

• Journal of KIISE:Information Networking
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• v.36 no.5
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• pp.456-469
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• 2009

We develop a new wireless link quality metric, ECOT(Estimated Channel Occupancy Time) that enables a high throughput route setup in wireless mesh networks. The key feature of ECOT is to be applicable to diverse mesh network environments where IEEE 802.11 MAC (Medium Access Control) variants are used. We take into account the exact operational features of 802.11 MAC protocols, such as 802.11 DCF(Distributed Coordination Function), 802.11e EDCA(Enhanced Distributed Channel Access) with BACK (Block Acknowledgement), and 802.11n A-MPDU(Aggregate MAC Protocol Data Unit), and derive the integrated link metric based on which a high throughput end-to-end path is established. Through extensive simulation in random-topology settings, we evaluate the performance of proposed link metric and present that ECOT shows 8.5 to 354.4% throughput gain over existing link metrics.

• Journal of Satellite, Information and Communications
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• v.10 no.3
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• pp.53-56
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• 2015

In this paper, we want provide improved services with faster transmission, IEEE 802.11n was standardized. A-MPDU (Aggregation MAC Protocol Data UNIT) is a vital function of the IEEE 802.11n standard, which was proposed to improve transmission rate by reducing frame transmission overhead. In this paper, we show the problems of TCP retransmission with A-MPDU and propose a solution utilizing the property of TCP cumulative ACK. If the transmission of an MPDU subframe fails, A-MPDU mechanism allows selective re-transmission of failed MPDU subframe in the MAC layer. In TCP traffic transmission, however, a failed MPDU transmission causes TCP Duplicate ACK, which causes unnecessary TCP re-transmission. Furthermore, congestion control of TCP causes reduction in throughput. By supressing unnecessary duplicate ACKs the proposed mechanism reduces the overhead in transmitting redundant TCP ACKs, and transmitting only a HS-ACK with the highest sequence number. By using the RACK mechanism, through the simulation results, it was conrmed that the RACK mechanism increases up to 20% compared the conventional A-MPDU, at the same time, it tightly assures the fairness among TCP flows.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.51-57
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• 2010

A dual-mode direct conversion receiver is developed in $0.13\;{\mu}m$ RF CMOS process for IEEE 802.11n based wireless LAN and IEEE 802.16e based mobile WiMAX application. The RF receiver covers the frequency band between 2.3 and 2.7 GHz. Three-step gain control is realized in LNA by using current steering technique. Current bleeding technique is applied to the down-conversion mixer in order to lower the flicker noise. A frequency divide-by-2 circuit is included in the receiver for LO I/Q differential signal generation. The receiver consumes 56 mA at 1.4 V supply voltage including all LO buffers. Measured results show a power gain of 32 dB, a noise figure of 4.8 dB, a output $P_{1dB}$ of +6 dBm over the entire band.