• Title/Summary/Keyword: IE3D

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Automated Generation of a Construction Schedule Based on the Work Method Template for 4D Simulation (4D 시뮬레이션을 위한 공법 템플릿 기반의 건설공정 자동 생성)

  • Song, Sung-Yol;Yang, Jeong-Sam;Myung, Tae-Sik
    • IE interfaces
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    • v.25 no.2
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    • pp.216-228
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    • 2012
  • BIM-based 4D simulation makes people easily understand complex construction process using 3D graphics model and helps them review and identify the construction schedule in each phase of the construction process. Moreover, 4D simulation can be used as reference data to determine the validity of the process in the design phase and will be utilized as a measure for checking the construction process. Therefore 4D simulation of construction improves efficiency of project management. However, current commercial applications available for 4D simulation do not provide sufficient functions for connection of 3D models and process information. In this paper, we propose an automated generation method through the definition of the process based on a work method template and developed the template based schedule generation system (TSGS).

Stepped Impedance LPF Using MCS Line with Ground (접지가 있는 MCS 선로를 이용한 스텝 임피던스 저역 필터)

  • Rhee, Seung-Yeop;Lee, Yong-Kook
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.19 no.11
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    • pp.1248-1253
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    • 2008
  • The MCS(Micro-Coplanar Strip) line with ground has been analyzed. The conformal mapping method is used to calculate the quasi-static effective dielectric constant and characteristic impedance of this MCS line. The computed results of the present work are found to be in good agreement when compared with the results obtained using commercial S/W, IE3D. And in this paper, the stepped-impedance low pass filter is designed and fabricated with MCS lines for improving the frequency responses. The LPF proposed structure has been also designed and implemented to have the sharp attenuation characteristics in stop band. The agreement between simulation and measurement results verify the implemented LPF.

Design of Dual frequency Inverted-F Antenna with Spur Line (스퍼 라인을 이용한 이중 주파수 역 F형 안테나의 설계)

  • 허문만;윤현보
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.13 no.7
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    • pp.702-708
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    • 2002
  • In this paper, we design the dual frequency antenna that could easily determine two operation frequencies by its inverted-F antenna structure and spur line length. The spur line is applied to the inverted-F antenna, in order to dual operation characteristics in PCS and cellular frequencies. It has designed by using the IE3D commercial software based on the moment method. As the designed antenna is fabricated and measured, you can see the results such as the return loss, the input impedance, the radiation patterns, and the gain. The size of this antenna is 40 mm$\times$14 mm$\times$9.4 mm, it is compact enough to use as an intenna. Also, This antenna can be used with cellular and PCS phone of domestic market.

Design of a compact and broadband PIFA using an additive short-circuit plate (추가 단락판을 이용한 소형 및 광대역 특성의 PIFA(Planar Inverted F Antenna) 설계)

  • 오경진;한영태;최재훈
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.8A
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    • pp.591-597
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    • 2003
  • In this paper, a compact and broadband PIFA(Planar Inverted F Antenna) which has an additive short-circuit plate along the patch length was designed. For more compact PIFA short-circuit Plate along the patch width is reduced and an additive short-circuit plate along the patch length is used to broaden the bandwidth. The effect of an additive-short-circuit plate along the patch length was verified in single band PIFA and also verified in dual-band PIFA. The commercial software, IE3D, was used to design a PIFA and its performance was verified by comparing simulated results with measurement results.

Performance Degradation of RF SOI MOSFETs in LNA Design Guide Line (RF SOI MOSFETs의 성능저하에 의한 LNA 설계 가이드 라인)

  • Ohm, Woo-Yong;Lee, Byung-Jin
    • 전자공학회논문지 IE
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    • v.45 no.2
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    • pp.1-5
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    • 2008
  • In this work, RF performance degradation due to hot carrier effects in SOI MOSFET have been measured and analyzed. The LNA that designed at $V_{GS}=0.8V$, f=2.5GHz, gain is 16.51dB and noise figure is 1.195dB. After stress at SOI, the LNA's gain and noise figure change of 15.3dB and 1.44dB with before stress.

Surface Modeling and 5-axis NC machining of Automobile Tire Model (자동차 타이어 모델의 곡면 모델링 및 5축 NC 가공)

  • Lee, Cheol-Soo
    • IE interfaces
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    • v.9 no.2
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    • pp.129-141
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    • 1996
  • Recently, the tire mold of a passenger car is made almost via aluminum casting, and it is necessary to prepare a master model of the tire for the casting. Because of the geometrical feature of tire, as well known, the master model must be machined by a 5-axis NC machine. The paper proposes a procedure to model and machine the master model. The approach includes (a) transformation of 2D drawing of tire into 3D geometry, (b) modeling surfaces of tire, and (c) inverse kinematics of a 5-axis NC machine. An implementation of the proposed procedure is also presented.

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Design and Implementation of Mutiple Slotted Dual-Band Square Patch Antenna with Circular Polarization (다수의 슬롯을 이용한 이중대역 원형편파 사각 패치 안테나 설계 및 구현)

  • Kim, Hyuck-Jin;Kim, Sung-Min;Yang, Woon-Geon
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.123-126
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    • 2005
  • In this paper, we propose a multiple slotted dual-band square patch antenna with CP(Circular Polarization) characteristic. And we present the simulation and measurement results of the design example. We designed a slotted patch antenna by using computer simulation program, Zeland IE3D, and then some tuning followed with measurements. Measured -10dB bandwidths of $S_{11}$ characteristic are 127MHz($2.346GHz{\sim}2.473GHz$) for the low-band, and 122MHz($3.379GHz{\sim}3.501GHz$) for the high-band, respectively. And measured maximum gains and half-power beamwidths are 6.94dBi, $72.95^{\circ}$ for the low-band at 2.30GHz, 5.78dBi, $76.51^{\circ}$ for the high-band at 3.45GHz, respectively.

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An Automated Design System for Ball-joint Parts of Automobiles (솔리드 모델러 기반의 볼 조인트 부품설계 자동화 시스템)

  • Kang, Jae-Gwan;Lee, Gwang-Il
    • IE interfaces
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    • v.16 no.spc
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    • pp.138-143
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    • 2003
  • In this paper, an automated design system for ball-joint parts based on 3-D solid modeler is developed. Parametric modeling and API provided by 3-D solid modeler is engaged to develope the system which consists of four main modules such as : 3-D part modeling, parts assembling, 2-D drafting, and database interfacing modules. The automated design system is implemented on a computer, and shows us that it shorten the design processing time which have taken over 5 hours to only few minutes.

Evaluation of R&D Projects in Electric Power Industry with Efficiency and Effectiveness (전력산업 R&D 프로젝트의 효율성 및 효과성 평가)

  • Park, Sung-Min;Kim, Heon;Baek, Dong-Hyun
    • IE interfaces
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    • v.22 no.3
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    • pp.192-204
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    • 2009
  • Based on the characteristics of 'Korean electric power industry R&D programs', this study proposes a new performance evaluation framework where electric power industry related R&D projects are scrutinized. The abovementioned R&D programs have their own goals and especially they emphasize the effectiveness as well as the efficiency of each subordinate R&D project. Hence, in this framework, a performance evaluation procedure is established and then a mathematical model is developed according to the procedure. The model calculates performance evaluation indices for a set of R&D projects integrating the effectiveness with the efficiency of each R&D project. In a case study with an empirical dataset, statistical significance is tested on the integrated performance evaluation indices of R&D projects regarding organizational types and program categories considered.

Quaternary D Flip-Flop with Advanced Performance (개선된 성능을 갖는 4치 D-플립플롭)

  • Na, Gi-Soo;Choi, Young-Hee
    • 전자공학회논문지 IE
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    • v.44 no.2
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    • pp.14-20
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    • 2007
  • This paper presents quaternary D flip-flop with advanced performance. Quaternary D flip-flop is composed of the components such as thermometer code output circuit, EX-OR gate, bias inverter, transmission gate and binary D flip-flop circuit. The designed circuit is simulated by HSPICE in $0.35{\mu}m$ one-poly six-metal CMOS process parameters with a single +3.3V supply voltage. In the simulations, sampling frequencies is measured around 100MHz. The PDP parameters and FOM we estimated to be 59.3fJ, 33.7 respectively.