• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제55권4호
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• pp.224-230
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• 2006

The conventional way to implement a bidirectional converter with boost/buck has been to use two general purpose PWM ICs with a single supply voltage. In this case, when one direction mode is in operation, the other is disabled and the output of the error amplifier of the disabled IC may be saturated to a maximum value or zero. Therefore, during mode transition, a circuit which can disable the switching operation for a certain time interval is required making it impossible to get a seamless transition. In this paper, the limitations of the conventional 42V/14V bi-directional DC/DC converter implemented with general current mode PWM ICs with a single supply voltage are reviewed and a new current mode PWM controller circuit with a dual voltage system is proposed. The validity of the proposed circuit is investigated through simulation. and experiments.

• 한국정보통신학회논문지
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• 제2권4호
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• pp.545-551
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• 1998

SSB, VHF 등의 장비로 구성된 무선국의 통신시스템은 지금도 중요한 정보전달의 수단으로 이용되고 있으며, 무선국의 통신권을 확보하기 위하여 산악, 도서등의 원거리에 설치되는 장비는 전용회선을 사용하여 원격제어로 송·수신을 행하고 있다. 그러나 무선국에서 다수의 사용자가 다수의 장비에 임으로 접속하고 운용을 해야하는 환경에서는 ICS(Integrated Communication System:통합통신시스템)의 회선접속 제어기가 요구된다. 본 논문에서는 ICS의 개발을 위하여 ASK(Amplitude Shift Keying) 변조방식에 의한 U(Push To Talk) 제어와 신호의 전송회로를 구성하여 실험하였고, 멀티-프로세싱에 의한 회선접속 제어기를 설계하여 통합 통신운용에 대한 알고리즘을 연구하였다. Keying에 의하여 PTT 신호를 단속하였고 지속되는 PTT 신호에 음성신호를 합성시켜 전송시키는 형태의 ASK 변조방식을 취하여 전송되도록 하였고, 회선접속 제어기는 master와 다수의 slave 프로세서를 멀티-프로세싱의 직렬데이터 전송방식으로 프로세서 상호간에 데이타가 전달되도록 구성하였다. 이에 따른 S/W 는 멀티-프로세싱의 인터럽트기법을 최대한 활용하여 원하는 회선에 정확히 접속되어 통신이 이루어지도록 설계하였다. 따라서 이 연구는 주파수 자원의 고갈과 통신량의 증가에 대한 대책의 일환으로 저비용의 시설로 재래식 장비의 운용 효율을 증대시키는 기술을 개발하는데 목적이 있다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2010년도 하계학술대회 논문집
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• pp.129-130
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• 2010

For the high power demand and N+1 redundancy, this paper presents the digital load share (LS) controller design and the implementation of paralleled phase-shifted full-bridge converters (PSFBC) used in distributed power systems. By adopting the digital control strategy, separately used ICs for PSFBC and LS control functions in analog systems can be merged into a cost-effective digital controller. To compensate and stabilize both PSFBC and LS loops with the direct digital design approaches, small-signal model of the system is derived in discrete-time domain. The steady-state and dynamic load sharing performances are also investigated. Experimental results from two 1.2 kW paralleled PSFBC modules are shown to verify the proposed work.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2007년도 하계학술대회 논문집
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• pp.274-276
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• 2007

In this paper, a low cost and high reliability control scheme is proposed for 400Hz UPS system operated in parallel. The proposed control scheme is consisted of two parts which are synchronization and load sharing control. The synchronization control is achieved by discrete logic ICs and analog circuit. The load sharing control is realized by current transformers (CTs) without any controller. Therefore, This proposed control scheme is rather simple and the cost may be decreased, compared with control scheme using expensive controller such as DSP and CAN. The practical feasibility of the proposed control scheme is proved by analysis and simulation.

• ETRI Journal
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• 제32권5호
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• pp.827-830
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• 2010

For an adaptive cruise control (ACC) stop-and-go system in automotive applications, three radar sensors are needed because two 24 GHz short range radars are used for object detection in an adjacent lane, and one 77 GHz long-range radar is used for object detection in the center lane. In this letter, we propose a single sensor-based 24 GHz radar with a detection capability of up to 150 m and ${\pm}30^{\circ}$ for an ACC stop-and-go system. The developed radar is highly integrated with a high gain patch antenna, four channel receivers with GaAs RF ICs, and back-end processing board with subspace based digital beam forming algorithm.

• Journal of Power Electronics
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• 제9권6호
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• pp.903-910
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• 2009

In this paper, a digital average current mode control using diode current sensing technique is proposed. Although the conventional inductor current sensing technique is widely used, the sensed signal of the current is negative. As a result, it requires an additional circuit to be applied to general digital controller ICs. The proposed diode current sensing method not only minimizes the peripheral circuit around the digital IC but also consumes less power to sense current information than the inductor current sensing method. The feasibility of the proposed technique is verified by experiments using a 500W power factor correction (PFC) boost rectifier.

• 전자공학회논문지A
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• 제31A권6호
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• pp.199-208
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• 1994

This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.

• 한국정보통신학회논문지
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• 제19권3호
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• pp.567-574
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• 2015

본 논문에서는 MCU(Micro Controller Unit) IC를 위한 50ns 256Kb EEPROM 회로를 설계하였다. 설계된 EEPROM IP는 기준전압을 이용한 차동증폭기 형태의 DB(Data Bus) 센싱 회로를 제안하여 읽기 동작시 데이터 센싱 속도를 빠르게 하였으며, DB를 8등분한 Distributed DB 구조를 적용하여 DB의 기생 커패시턴스 성분을 줄여 DB의 스위칭 속도를 높였다. 또한 기존의 RD 스위치 회로에서 5V 스위치 NMOS 트랜지스터를 제거함으로써 읽기 동작 시 BL의 프리차징 시간을 줄여 액세스 시간을 줄였고 데이터 센싱 시 DB 전압과 기준전압 간의 전압차 ${\Delta}V$를 0.2VDD 정도 확보하여 출력 데이터의 신뢰도를 높였다. 매그나칩반도체 $0.18{\mu}m$ EEPROM 공정으로 설계된 256Kb EEPROM IP의 액세스 시간은 45.8ns 이며 레이아웃 면적은 $1571.625{\mu}m{\times}798.540{\mu}m$이다.

• Journal of Power Electronics
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• 제10권1호
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• pp.97-105
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• 2010

This paper presents the modeling, control and simulation of an interconnection system (ICS) of cascaded distributed generation (DG) modules for both grid-tied and stand-alone operations. The overall configuration of the interconnection system is given. The interconnection system consists of a cascaded DC/DC boost converters and a DC/AC inverter. Detailed modeling of the interconnection system incorporating a cascaded architecture has not been considered in previous research. In this paper, suitable control systems for the cascaded architecture of power electronic converters in an interconnection system have been studied and modeled in detail. A novel control system for DC/DC boost converters is presented based on a droop voltage controller. Also, a novel control strategy for DC/AC inverters based on the average large signal model to control the aggregated DG modules under both grid-tied and stand-alone modes is demonstrated. Simulation results indicate the effectiveness of the proposed control systems.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.129-140
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• 2017

In this paper, a $4{\times}32$-channel neural recording system capable of acquiring neural signals is introduced. Four 32-channel neural recording ICs, complex programmable logic devices (CPLDs), a micro controller unit (MCU) with USB interface, and a PC are used. Each neural recording IC, implemented in $0.18{\mu}m$ CMOS technology, includes 32 channels of analog front-ends (AFEs), a 32-to-1 analog multiplexer, and an analog-to-digital converter (ADC). The mid-band gain of the AFE is adjustable in four steps, and have a tunable bandwidth. The AFE has a mid-band gain of 54.5 dB to 65.7 dB and a bandwidth of 35.3 Hz to 5.8 kHz. The high-pass cutoff frequency of the AFE varies from 18.6 Hz to 154.7 Hz. The input-referred noise (IRN) of the AFE is $10.2{\mu}V_{rms}$. A high-resolution, low-power ADC with a high conversion speed achieves a signal-to-noise and distortion ratio (SNDR) of 50.63 dB and a spurious-free dynamic range (SFDR) of 63.88 dB, at a sampling-rate of 2.5 MS/s. The effectiveness of our neural recording system is validated in in-vivo recording of the primary somatosensory cortex of a rat.